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CONTROL
REGISTER
BIT ASSIGNMENT
TABLE
Bit
Signal
7
TR
6
BREAK
5
IE
4
3
WLS2
WI.SI
2
SBS
I
EPE
0
Pl
Bil Signal:
Func1ion
12
0
PARl1Y
INHIBIT
(Pl):
When
sea
high
parity gcneralion
:llld vcrificalion
are lnhibiled
and
the PE
Status bit
is
held
low.
If parity is
inhibited
the stop bits(s) will
immediately follow
1he last da1a bil
on
1ransmission.
and EPE
is
ignored.
EVEN
PARITY
ENABLE (EPE):
When
set
high. even
parity
is
generated
by
the transmillcr
and checked by the
receiver.
Wilen
low, odd
parity
is
selected.
2
STOP BIT
SELECT
(SllS):
Sec
table
below.
3
WORD LENGTH
SELECT
I (WLSI):
See
table below.
4 WORD LENGTH SEUiCT
2 {WLS2):
See 1able
below.
Bit 4
Bil
3
Bit 2
WLS2
WLSI
SBS
0
0
0
0
0
1
0
I
0
0
I
1
0
0
0
1
0
Function
5
data
bits,
I
stop bit
S
data bias,
J.S stop
bits
6
da
1a
bias, I stop bit
6
data
bits,
2
stop
bits
7
data
bits,
I
stop bit
7 data
bias,
2
stop bits
8
dala bits,
1
stop bit
8 da1a
bits,
2 stop
bits
Fig.
3
-
Control
Rcgistar
bit
assignment.
5
INTERRUPT
ENABLE
(IE):
When set high
THRE.
DA.
THRE
·
TSRE, CTS.
:llld
PSI interrupts are
enabled (see ln1errupt
Conditions. Table
II).
6
TRANSMIT BREAK
( BREAK):
Holds SDO
low
when set.
Once
the
break
bit in the control
regis1er
has been
set
high.
SDO
will
s1ay low until
the
break
bil
is
reset low and
one of the following
occurs:
CLEAR
goes
low;
CTS
&oes
high
;
or
a
word
is
transmilled. (The 1ransmit1ed word wil.I nol be
valid
since
there
can
be
no
starl bit
if SDO
is
already
low.
SDO
r;.1n
be sci
high
without
intermediate
transitions
by
trans·
milling
a
word
consisting
of
all
zeros).
7
TRANSMIT
REQUEST (TR):
When
set
high,
RTS
is
set low and
data transfer
through
the
1ransmit1cr
is
initiated
by
the
ini tial
THRE
interrupt. (When loading the Control
Register from
1he
bus,
this
(TR)
bit
inhibi1s
chang-
ing
of other control Oip.nops.)
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