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All and
more about Sharp
PC-1500
at http:f/www.PC-1500.info
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TP9
~~~~~~~~~~~~~~
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ASEL
~~~~~~~~~v-~~~~-1
•~~~...,._~--..,;,...-~~~~
II
*
READ IS THE OVER LAP OF
CS
!.
CS3.
RD/WR
•
I
AND
CS2
•
0
Fig.
6
-
MODE
I cpu inte1facc
(READ)
timing diagram
TABLE
2·1nterrupt
Set and
Reset
Conditions
SET*
(INT
=
LOW)
RESET (INT
=
HIGll)
CAUSE
CONDITION
TIM
E
DA
Read
of datn
TPB
leading
edge
(Receipt
of
data}
THRE*
Read
or
Stntus
or
TPB
leading edge
(Ability to
reload)
write of
character
THRE
•
TSRE
Read
of status
or
TPB
leading edge
(Transmitter done)
write
of
character
PSI
Read
of
status
TPB
trailing edge
(Negative edge)
CTS
Read of
st
:it
us
TPB leading
edge
(Positive
edge
when
TH RE
·
TSRE)
•
Interrupts
will occur
o
nly
after lhe
1£
bit
in the
Co ntrol
Rcgislcr
(sec
F ig.
3)
has
been
set.
•
TH
RE will cause
an interrupt only
:after the TR bit
in
the
Control Register
(see Fig.
3)
has been se
t.
FUNCTIONAL DEFINITIONS FOR CDP1854A
TERMINALS
~1
0DE
I
SIGNAL:
FUNCTION
vDD:
Positive
supply
voltage
MODE
SELECT (MODc):
A higll·level voltage at this input selects
MODE I
operation.
VSS:
Ground
CHIP SELECT
2
(CS2):
A
low·lcvcl voltage at
this
input
ll>gether
with
CS
I
and
CS3
selects the
COPI 8S4A
UART.
RECEIVER
BUS
(
R BUS
7
· R BUS
0):
16
Receiver
parallel data outputs (may be
ex·
ternally connected
to corresponding
transmit·
tcr
bus
terminals).
INTERRUPT
(INT):
A low·lcvel voltage
al
this
output indicates
the
p1escncc
of one of
more
of
the
interrupt
con·
ditions listed
in
Table
2.
FRAMI
NG
ERROR
(FE):
A
high-level
voltage at this
output
indicatt!S
that
the
1eceivecl character
has no valid
stop
bit
,
i.e
..
the
bit
following
the
paii
ty
bit
( if
programmed)
is
not
a
high·levcl volt:tgc. This
ou tput
is
updated
each
lime
a
chnraclcr
is
transferred
10
the
Receiver
Holding
Register.
PARITY
ERROR
or
OVERRUN
ERROR
(PE{OE):
A hig)l·lcvcl voltage at this output
indicates
that
either the PE or
OE bit in the
Sll1Us
Register
has
been
set
(see Status
Register
Bit
Assignment
,
F
ig.
4).
REGIST
ER
SELECT
( RSEL):
This
Input
is
used
to
choose
eit her
the
Control/Statlls
Register
(high input) or the
transrnltter{receiver
data
registers
(low
input)
according
10
the lruth table
in
Table
I.
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