JVC KD-LH3101 Service Manual page 32

Cd receiver
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4.4
BR24L32F-W-X (IC703) : EEPROM
• Pin layout
Vcc
WP
A0
A1
• Block diagram
A0
1
A1
2
A2
3
TE
L 13942296513
GND
4
4.5
BU4066BCFV-X (IC131) : Quad analog switch
• Pin layout & Block diagram
VDD
14
www
1
I/O1
.
1-32 (No.49843)
http://www.xiaoyu163.com
SCL
SDA
A2
GND
32kbit EEPROM array
12bits
Address
Slave word
12bits
decoder
address register
START
Control logic
High voltage generator
Vcc level detect
C1
C4
13
12
2
3
x
ao
u163
y
O/I1
O/I2
i
http://www.xiaoyu163.com
2 9
8
• Block diagram
Symbol
I/O
A0,A1,A2
I
Slave address set
GND
-
Ground (0V)
SDA
I/O
Slave and word address
Serial data input, serial data output
SCL
I
Serial clock input
WP
I
Write protect input
VCC
-
Power supply
8bits
Data
register
STOP
ACK
Q Q
3
6 7
1 3
1 5
I/O4
O/I4
O/I3
11
10
9
4
5
6
co
I/O2
C2
C3
.
9 4
2 8
Function
8
Vcc
7
WP
6
SCL
0 5
8
2 9
9 4
2 8
5
SDA
I/O3
8
m
7
Vss
9 9
9 9

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