Es3880 Video Cd Processor Chip; Visba Video Pc Processor Chip Pin Description - Philips FW-M355 Service Manual

ES3880 VIDEO CD PROCESSOR CHIP

80 79 78 77 76 75 74 73 72 71 70
VPP 81
LA12 82
LA13 83
LA14 84
LA15 85
LA16 86
LA17 87
ACLK 88
AOUT/SEL_PLL0 89
Visba ES3880
ATCLK 90
ATFS/SEL_PLL1 91
Video CD PC
DA9/DOE# 92
93
AIN
ARCLK 94
ARFS 95
96
TDMCLK
TDMDR 97
TDMFS 98
CAS# 99
VSS 100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Processor
LA[17:0]
Interface
LD[7:0]
LCS3#, LCS#[1:0]
LWR#
RISC
LOE#
Processor
ACLK
ATCLK
Serial
AIN
Audio Serial Audio
AOUT
ARFS
Interface Interface
ATFS
ARCLK
SEL_PLL[1:0]
TDM
TDM
TDMCLK
Interface
Interface
TDMDR
TDMFS
Visba Video CD PC Block Diagram
8-4
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
ESS
100-pin PQFP
20 21 22 23 24 25 26 27 28 29 30
RAS#
DA[8:0]
DRAM Interface
DBUS[15:0]
Huffman
DOE#
Decoder
DWE#
2Kx32 ROM
CAS#
512x32 SRAM
AUX[7:0]
MPEG
Processor
64x32 ROM YUV[7:0]
PCLK2X
PCLK
32x32 SRAM
Video Output VSYNC
HSYNC
Registers
On Screen
Display
CPUCLK
RESET#
DRAM DMA
Controller

VISBA VIDEO PC PROCESSOR CHIP PIN DESCRIPTION

Name Number
VDD 1, 31, 51
RAS# 2
50 VSS
49 AUX4
DWE# 3
48 AUX3
DA[8:0] 12:4
47 AUX2
DBUS[15:0] 28:13
46 AUX1
RESET# 29
45 AUX0
VSS 30, 50, 80, 100
44 PCLK
43 PCLK2X
YUV[7:0] 39:32
42 CPUCLK
41 HSYNC
VSYNC 40
40 VSYNC
HSYNC 41
39 YUV7
CPUCLK 42
38 YUV6
37 YUV5
PCLK2X 43
36 YUV4
PCLK 44
35 YUV3
34 YUV2 AUX[7:0] 54, 52, 53,
33 YUV1 49:45
32 YUV0
LD[7:0] 62:55
31 VDD
LWR# 63
LOE# 64
LCS[3,1,0]# 65,66,67
LA[17:0] 87:82, 79:68
VPP 81
ACLK 88
AOUT/ 89
SEL_PLL0
DRAM ATCLK 90
ATFS/ 91
SEL_PLL1
AUX DA9/DOE# 92
AIN 93
Screen
ARCLK 94
Display
ARFS 95
TDMCLK 96
TDMDR 97
TDMFS 98
Misc.
CAS# 99
8-4
I/O Definition
I Voltage supply for 3.3 V.
O DRAM row address strobe (active low).
O DRAM write enable (active low).
O DRAM multiplexed row and column address bus.
I/O DRAM data bus.
I System reset (active low).
I Ground.
O Y is luminance, UV are chrominance data bus for screen video interface. YUV[7:0] for 8-
bit YUV mode.
I/O Vertical sync for screen video interface, programmable for rising or falling edge.
I/O Horizontal sync for screen video interface, programmable for rising or falling edge.
I RISC and system clock input.
CPUCLK is used only if SEL_PLL[1:0] = 00.
I/O Pixel clock; two times the actual pixel clock for screen video interface.
I/O Pixel clock qualifier in for screen video interface.
I/O Auxiliary control pins (AUX0 and AUX1 are open collectors).
I/O RISC interface data bus.
O RISC interface write enable (active low).
O RISC interface output enable (active low).
O RISC interface chip select (active low).
O RISC interface address bus.
I Digital supply voltage for 5 V.
I/O Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz, and 18.432 MHz).
O Dual-purpose pin. AOUT is the audio interface serial data output
I Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK
for the Visba:
00 = bypass PLL.
01 = 54 MHz PLL.
10 = 67.5 MHz PLL.
11 = 81 MHz PLL.
I/O Audio transmit bit clock.
O Dual-purpose pin. ATFS is the audio interface transmit frame sync.
I Pins SEL_PLL[1:0] select phase-lock loop (PLL) clock frequency CPUCLK for the Visba.
See the SEL_PLL0 pin above for the settings.
O Dual purpose pin: DRAM output enable (active low)/DRAM multiplexed row and column
address bus.
I Audio interface serial data input.
I Audio receive bit clock.
I Audio interface receive frame sync.
I TDM interface serial clock.
I TDM interface serial data receive.
I TDM interface frame sync.
O DRAM column address strobe bank 0 (active low).