Audio Board - ViewSonic VLCDS26104-3W Service Manual

multiplied seven times ( ) and then used to unload the data registers in 7-bit slices and
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to
LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control. The data
bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only user intervention is the possible use of the
shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output
drivers for lower power consumption. A low-level signal on SHTDN clears all internal
registers to a low level.
1.5 DDC 1/2 B
IC600 (24LC02) & IC602 (24LC21A) can continuously transmit its extended identification,
"EDID" using DDC1 communication channel. In addition, the monitor can respond to a request
for EDID, or complete VDIF, to be transmitted using DDC2, level B commands. Pin6 SCL is
clock input for DDC 2B, pin5 SDA for data input, and pin7 VCLK is clock input for DDC1.
In DDC1 data transfer (UNI-directional mode), the VCLK input pin is used as an input
clock for data transmission and SDA output pin is used as serial data line the SCL pin will
hold high. The DDC2B node (BI-directional mode) BUS consists of two wires. SCL is for
the data transmission clock and SDA is for the data line.

2. Audio Board

2.1 Audio processor
ICA2 (PT2313L) is a four-channel digital audio processor utilizing CMOS
Technology .Volume, Bass, Treble, Balance, Front/Rear Fader Processor are incorporated
into a single chip. Loudness function and Selectable input gain are also provided to build a
highly effective electronic Audio processor having the highest performance and reliability
with the least external components. and all functions are programmable using the IIC BUS
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