Hyundai ImageQuest L70A Technical & Service Manual page 22

L70A Technical Service Manual
DS90C387/DS90CF388
MC68HC705BD7B
Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA
General Description
The DS90C387/DS90CF388 transmitter/receiverpair is de-
signed to support dual pixel data transmission between Host
and Flat Panel Display up to QXGA resolutions. The trans-
mitterconverts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL
data into 8 LVDS (Low Voltage Differential Signalling) data
streams. Control signals (VSYNC, HSYNC, DE and two
user-defined signals) are sent duringblankingintervals. At a
maximumdual pixel rate of 112MHz, LVDS data line speed is
672Mbps, providing a total throughput of 5.38Gbps (672
Megabytes per second). Two other modes are also sup-
ported. 24-bit color data (single pixel) can be clocked into the
transmitterat a maximumrate of 170MHz. In this mode, the
transmitter provides single-to-dual pixel conversion, and the
outputLVDS clock rate is 85MHz maximum.The thirdmode
provides inter-operabilitywithFPD-Link devices.
The LDI chipset is improved over prior generations of
FPD-Link devices and offers higher bandwidthsupport and
longer cable drive with three areas of enhancement. To
increase bandwidth, the maximum pixel clock rate is in-
creased to 112 (170) MHzand 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additionaloutputcurrent
during transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided to re-
duce ISI (Inter-Symbol Interference). Withpre-emphasis and
DC balancing, a low distortioneye-pattern is providedat the
receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pairskew of up
to +/-1 LVDS data bit time (up to 80 MHzClock Rate). These
three enhancements allow cables 5 to 10+ meters in length
to be driven. (Continued)
Generalized Block Diagram
Features
Complies withOpenLDI specification for digitaldisplay
•
interfaces
32.5 to 112/170MHzclock support
•
Supports SVGA through QXGA panel resolutions
•
Drives long, low cost cables
•
• Up to 5.38Gbps bandwidth
Pre-emphasis reduces cable loading effects
•
DC balance data transmission providedby transmitter
•
reduces ISI distortion
•
• Cable Deskew of +/-1 LVDS data bit time (up to 80
MHz Clock Rate) of pair-to-pairskew at receiver inputs;
intra-pairskew tolerance of 300ps
Dual pixel architecture supports interface to GUI and
•
timingcontroller; optional single pixel transmitter inputs
support single pixel GUI interface
•
Transmitter rejects cycle-to-cycle jitter
• 5V tolerant on data and control inputpins
Programmable transmitter data and control strobe select
•
(rising or falling edge strobe)
• Backward compatible configurationselect withFPD-Link
Optional second LVDS clock for backward compatibility
•
w/FPD-Link
Support for two additionaluser-defined control signals in
•
DC Balanced mode
• Compatible withTIA/EIA - LVDS Standard
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DS100073-1