Mpeg Encode Block Diagram - Sony DCM-M1 Service Manual

3-5. MPEG ENCODE BLOCK DIAGRAM

MAIN BOARD (2/7)
(SEE PAGE 4-33, 59)
MPEG2 ENCODER
IC8601
113
VE0 – VE7
MEC0 – MEC7 l
120
103
•
104
VDD0 – VDD7
SYS_MVP0 – SYS_MVP7
•
106
l
111
MCLK_BUFF CLK
175
FSY_INT FSY
7
122
94
TO A/V DATA CONTROL,
l
VIDEO OUT
99
VDI0 – VDI7
•
(SEE PAGE 3-8)
101
l
102
128
ENDT0 – ENDT7
l
135
MPEG2 VIDEO PROCESSOR
IC8701
2
ENDT0 – ENDT7
l
9
•
11
FSY
1
CLK
112
65
l
68
VOUT0 – VOUT7
•
70
l
73
SYS_BITI
SYS_BITO
HANDO
HANDI
05
2 4 5 7 8 10 11 13 31 33 34 36 37 39 40 42 22 – 27
• • • • • • • • • • • • • • • • •
17 18 19 68
45 47 48 50 51 53 54 56 74 76 77 79 80 82 83 85 60 66
• • • • • • • • • • • • • • • –
1 – 4 6 – 8 10 11 13 – 16 18 41 – 43 45 – 48
• • • • • • •
59 58 57 84
19 21 – 28 30 – 32 44 – 38 40
• • • • • 50 – 55
DRAM INTERFACE
MOTION MB DATA
ESTIMATION PROCESSOR
ADAPTIVE PREFILTER
ENCODE SEQUENCE
CONTROL
CHROMA POSTFILTER
3.52 Vp-p
27 MHz
16M EDO DRAM REC/PB 16M EDO DRAM
IC8702 IC8703
2 5 7 10 21 24 2 5 7 10 21
– • – • – • – • – •
17 18 34 35
•
41 – 44 • 46 – 49 27 – 32 41 – 44 • 46 – 49 27
12 14 16 19 21 24 49 50 52 57
– • – • – • • • –
63 61 62
26 – 36 • 38 – 43 • 45 – 48 59 60
• •
DRAM INTERFACE
VARIABLE LENGTH
ENCODER
CODING
LOCAL
VARIABLE LENGTH
DECODER
DECODING
BIT STREAM MANAGER
106 107 108 110
3-9
64M SDRAM
IC8602
137 138
•
•
140 – 143
•
D0-D15
145 – 148 850D0 – 850D15 850D0 – 850D15
•
150 – 153
•
155 • 156
157
•
158
A0 – A5
850A1 – 850A6 850A0 – 850A6
•
160
l
163
XRST
173
PLLI(FN)
62
XIMB
170
BS
164
XCS
168
XRD
166
XWR
167
4JACK_DET
S_JACK_DET
C_OUT_OFF
S_OUT_OFF
11 X2CK 2D 12
2Q 9
D-FF
IC8020(2/2)
24
– •
17 18 34 35
•
– 32
111
RST
•
TRST
118
XWR
92
XRD
91
XCS
90
84
A0 – A5
l 850A0 – 850A5
89
75
D0 – D7
l 850D0 – 850D7
82
MPEG2 RATE CONTRL
&
SYSTEM CONTROL
IC8501
127
ADA_REST
TO AUDIO
l 9
ADA_REST 19
134 D0
AT_REST (SEE PAGE 3-17)
• l AT_REST 20
D15
136 AT_EXEC
AT_EXEC 47
l
143 AT_STRO
AT_STRO 48
AT_INSL
AT_INSL 49
AT_MUTE
AT_MUTE 50
AT_REC
AT_REC 51
119 A0
AT_ATRAC2
AT_ATRAC2 52
l l
125 A6 AT_LEVEL3
AT_LEVEL3 53
SP_BEEP
SP_BEEP 7
HP_BEEP
4 MEC_RESET HP_BEEP 8
SP_NMUTE
80 CLK_OUT SP_NMUTE 88
AMUTE
1 XIMB AMUTE 89
SP_VDD
87 BS SP_VDD 90
PWR_DWN
98 XCS1 PWR_DWN 91
MIC_ATT
94 XRD 110
MIC_ATT
XWIND
95 XWR XWIND 111
97 XCS2
MIC_JACK_DET
MIC_JACK_DET 104
HP_JACK_DET
106 4JACK_DET HP_JACK_DET 105
W_JACK_DET
103 S_JACK_DET W_JACK_DET 107
CN8007
101 C_OUT_OFF
(1/3)
102 S_OUT_OFF
ETHER_RESET
ETHER_RESET 23 32
5 MVP_RESEM
CN4313
(2/3)
RIGHT
RIGHT 58 1
DOWN
59 2
DOWN
V_REC_LED
TO MODE CONTROL
10
V_REC_LED 78
A_REC_LED (SEE PAGE 3-24)
A_REC_LED 79
DRV_RESET
TO MD SERVO
11
DRV_RESET 22
(SEE PAGE 3-14)
DEV_RESET
TO SYSTEM CONTROL
12
XRESET 71
RATE_RTS (SEE PAGE 3-15)
RATE_RTS 33
RXDO 40
RATE_TX
• •
RX_SYS 43
TXDO 39
RATE_RX
• •
TX_SYS 40
RATE_CTS
RATE_CTS 6
1.12 Vp-p
6.6 MHz
REC/PB
64
X1
X8501
6.6MHz
X2 63
3-10
DCM-M1
TO ETHER
G
INTERFACE
(SEE PAGE 3-25)
TO LCD
H
(SEE PAGE 3-19)