Pt8300 (Uic03, Uic04) : Dram - JVC MX-GA77 Service Manual

MX-GA77

PT8300 (UIC03, UIC04) : DRAM

1.Pin layout
VSS 1 28 VDD
/RESET 2 27 PULLUP
CLK 3 26 DI1
LATCH 4 25 DO2
P15 5 24 P0
P14 6 23 P1
P13 7 22 P2
P12 8 21 P3
P11 9 20 P4
P10 10 19 P5
P9 11 18 P6
P8 12 17 P7
LATCH0 13 16 DI2
CLK0 14 15 DO1
2.Block diagram
27
PULLUP
28
VDD
1
VSS
4
LATCH
3
CLK
26
DI1
/RESET
2
/RESET
14
CLKO
16
DI2
13
LATCH0
25
DO2
15
DO1
3. Pin function
Pin No. Pin Name
1 VSS
2 /RESET
3 CLK
4 LATCH
5-12 P15~P8
13 LATCHO
14 CLKO
15,25 DO1, DO2
26,17 DI1, DI2
17-24 P7~P0
27 PULLUP
28 VDD
1-42
LATCH
RESET
CLK
DI
CLK
DI
I/O Function
- Ground
I Reset pin
I Clock input pin
I Latch input pin
I/O Parallel data I/O pins
O Latch output pin
O Clock output pin
O Serial data output pins
I Serial data input pins
O Parallel data output pin
I P8 to P15 control pin for internal pull-up resistor
When P8 to P15 are in the output state, the PULLUP pin must be connected to VDD.
When P8 to P15 are in the input state, the PULLUP pin must be connected to VSS.
- Power supply pin
P0 P1 P2 P3 P4 P5 P6 P7
O0
LATCH 16-BIT
I0
Q0
SHIFT REGISTER1: 16-BIT SHIFT REGISTER SERIAL TO PARALLEL
RESET
D0
SHIFT REGISTER2: 16-BIT SHIFT REGISTER SERIAL TO PARALLEL
P8 P9 P10 P11 P12 P13 P14 P15
O7 O8 O15
I7 I8 I15
Q15
DO
D15
DO