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The first chipset settings deal with CPU access to dynamic random access memory (DRAM).
The default timings have been carefully chosen and should only be altered if data is being
lost. Such a scenario might well occur if your system has mixed speed DRAM chips installed
so that greater delays may be required to preserve the integrity of the data held in the slower
memory chips.
Selecting Advanced Chipset Features on the main program screen displays this menu:
Figure 4-4: BIOS – Advanced Chipset Features
System BIOS cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The available choices are Enabled, Disabled.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h, resulting in better
video performance. However, if any program writes to this memory area, a system error may
result. The choices:
Enabled, Disabled.
On-Chip VGA
By default, the On-Chip VGA or chipset-integrated VGA is Enabled.
On-Chip Frame Buffer Size
The On-Chip Frame Buffer Size can be set as 1, 4, 8, 16 or 32MB. This memory is shared
with the system memory.
Boot Display
Boot Display determines the display output device where the system boots. The options are
Auto, CRT, LFP, and CRT+LFP.
D E L T A
C O M P O N E N T S
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