JVC GR-D370UC Schematic Diagrams page 14

MAIN(MONI/VF) SCHEMATIC DIAGRAM
TO REG
REG_8.5V
TO CPU
VF_CS
AU_LV_OUT
TO MAIN IF(CN103),CPU,AUDIO
AU_LV_CLK
LCD_R
TO VIDO LCD_G
LCD_B
VDCVF
TO MAIN IF(CN103),VIDEO
HDCVF
REG_3.1V
TO CDS/TG,REG REG_15V
TO CPU RGB_CTL
REG_4.8V
TO MAIN IF(CN103) LCD_3V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
L7802
NQR0602-001X
48 47 46
L7803
µ
100
49 VCC1
C7811
C7812
4.7
50 DSDOUT
1
51 NC
C7813
52 VREG
1
C7814
53 RIN
0.1
C7815
54 GIN
0.1
C7816
55 BIN
0.1
C7817
56 RESET
22000p
57 SYNC IN
C7818
58 VSEP TC
OPEN
59 VDIN
60 HDIN
61 TEST1
62 TEST2
TL7801
63 CLPIN
64 GND1
TL7802
1 2 3
L7801
0
R7721 0
R7715
OPEN
1 4 Q7704
XP4311-W
UMD3N-W
2 5
6 3
IC7701
OPEN
GND IN OUT
3 2 1
C7711 C7712
OPEN OPEN
45 44 43 42 41 40 39 38 37 36 35 34 33
VSS2 32
VD 31
ENB 30
XENB 29
CKV1 28
CKV2 27
STV 26
XSTV 25
IC7801
DSG 24
LV4141W-E-X
XDSG 23
TEST7 22
TEST6 21
CKH1 20
CKH2 19
STH 18
XSTH 17
4 5 6 7 8 9 10 11 12 13 14 15 16
L7701
0
T
C7701
NBP41EM-475X-B
6 3
2
1 4
(No.YF124)2-25 2-26(No.YF124)
C7819 C7820 C7821 C7822
R7803
OPEN OPEN OPEN OPEN
1k
R7804
1k
R7805
1k
R7806
1k
R7807
1k
R7808
1k
C7823 C7824
OPEN OPEN
R7809
680
R7810
680
R7811
1k
R7812
1k
C7825 C7826 C7827 C7828
47p 47p OPEN OPEN
Q7701 6 3 Q7702 6 3 Q7703
PUMX1-W PUMX1-W PUMX1-W
5 2 5 2 5
1 4 1 4
0 1 MAIN(MONI/VF)
yf124_y20401001a_rev0.1
VDD_VF
TO MAIN IF(CN7801)
DSD
CVF_R
CVF_G
TO MAIN IF(CN102,7801)
CVF_B
COM_VF
ENB
XENB
CKV1
CKV2
STV
TO MAIN IF(CN7801)
XSTV
DSG
XDSG
CKH1
CKH2
STH
XSTH TO MAIN IF(CN102,7801)
CVF_RPD TO MAIN IF(CN102)
MON_G
MON_R TO MAIN IF(CN103)
MON_B