Pin No.
Pin Name
57
XPDI
58
VDDS
59, 60
HA0, HA2
61
VSS
62, 63
HCS0, HCS1
64
VDD
65
DASP
66 to 69
MDB0 to MDB3
70
VSS
71
MDB4
72
VDD5V
73 to 75
MDB5 to MDB7
76
XMWR
77
VDD
78
XRAS
79, 80
MA0, MA1
81
VSS
82 to 87
MA2 to MA7
88
VDD
89
MA8
90
VSS
91
MA9
92
MNT1
93
MNT2
94
XMOE
95
XCAS
96, 97
MDB8, MDB9
98
VSS
99
MDBA
100
VDD
101, 102
MDBB, MDBC
103
VDD5V
104 to 106
MDBD to MDBF
107
GFS
108
VSS
109
APEO
110
VDD
111
DASYO
112
GNDA5
113, 114
ASF1, AFS2
115
DASYI
116
RFDCC
117
RFIN
118, 119
VCCA5, VCCA4
120
VCOR1
121
VCOIN
122, 123
GNDA4, GNDA3
124
LPF5
125
VC1
126, 127
LPF2, LPF1
I/O
I/O
Not used
—
Power supply terminal (+5V) (digital system)
I
Not used
—
Ground terminal (digital system)
I
Not used
—
Power supply terminal (+3.3V) (digital system)
I/O
Not used
I/O
Two-way data bus with the D-RAM
—
Ground terminal (digital system)
I/O
Two-way data bus with the D-RAM
—
Power supply terminal (+5V)
I/O
Two-way data bus with the D-RAM
O
Write enable signal output to the D-RAM
—
Power supply terminal (+3.3V) (digital system)
O
Row address strobe signal output to the D-RAM
O
Address signal output to the D-RAM
—
Ground terminal (digital system)
O
Address signal output to the D-RAM
—
Power supply terminal (+3.3V) (digital system)
O
Address signal output to the D-RAM
—
Ground terminal (digital system)
O
Address signal output to the D-RAM
O
EEPROM ready signal output to the mechanism controller
O
Operation clock signal output for PSP physical disc mark detection to DSD decoder
O
Output enable signal output to the D-RAM
O
Column address strobe signal output to the D-RAM
I/O
Two-way data bus with the D-RAM
—
Ground terminal (digital system)
I/O
Two-way data bus with the D-RAM
—
Power supply terminal (+3.3V) (digital system)
I/O
Two-way data bus with the D-RAM
—
Power supply terminal (+5V)
I/O
Two-way data bus with the D-RAM
O
Guard frame sync signal output to the mechanism controller
—
Ground terminal (digital system)
O
Absolute phase error signal output
—
Power supply terminal (+3.3V) (digital system)
O
RF binary signal output
—
Ground terminal (analog system)
—
Filter connected terminal for selection the constant asymmetry compensation
I
Analog signal input after integrated from the RF binary signal
I
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
I
RF signal input from the DVD/CD RF amplifier
—
Power supply terminal (+3.3V) (analog system)
—
VCO oscillating range setting resistor connected terminal
I
VCO input terminal
—
Ground terminal (analog system)
O
Signal output from the operation amplifier from PLL loop filter
I
Middle point voltage (+1.65V) input terminal
I
Inverted signal input to the operation amplifier from PLL loop filter
HCD-GX90D/RV800D
Description
59