Sharp CD-C831W Service Manual page 42

CD-C831W
IC2 VHiLC78622N-1: Servo/Signal Control (LC78622NE) (2/2)
Pin
Terminal Name Input/Output
No.
47* SBSY
48* EFLG
49* PW
50* SFSY
51 SBCK
52* FSX
53 WRQ
54 RWC
55 SQOUT
56 COIN
57 CQCK
58 RES
59* TEST11
60* 16M
61 4.2M
62 TEST5
63 CS
64 TEST1
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
DEFI
Slice level
control
EFMIN
Sync detection
FSEQ
EFM demodulation
CLV+
C L V
Digital servo
CLV-
V/P
PW
Subcode division
SBCK
QCRC
SBSY
SFSY
CS
WRQ µ C O M
Interface
SQOUT
CQCK
COIN
Servo commander
RWC
Output Sub-code clock sync signal output terminal.
Output C1, C2, single, double correction monitor terminal.
Output Sub-code P, Q, R, S, T, U, and W output terminal.
Output Sub-code frame sync signal output terminal. Falling occurs when the sub-code is in standby state.
Input Sub-code read clock input terminal. Schmidt input (When this terminal is not used, connect it to 0V.)
Output 7.35 kHz sync signal (frequency-divided from crystal oscillation) output terminal.
Output Sub-code Q output standby output terminal.
Input Read/Write control input terminal. Schmidt input.
Output Sub-code Q output terminal.
Input Command input terminal from microcomputer.
Input Command input taking-in clock or sub-code taking-out (from SQOUT) clock input terminal.
Schmidt input
Input LSI resetting input terminal. When power is turned on, once "L" is set.
Output Output terminal for test. Use this terminal in open state (usually "L" output).
Output 16.9344 MHz output terminal.
Output 4.2336 MHz output terminal.
Input Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V.
Input Chip selection input terminal. Pull-down resistor built-in.
In noncontrol state connect this terminal to 0V.
Input Input terminal for test. Pull-down resistor is not provided. Be sure to connect this terminal to 0V.
VCO colck oscillation
clock control
General-use port
Figure 42 BLOCK DIAGRAM OF IC
Function
2 K x 8 b i t
R A M
Flag processing of C1/C2
error detection and correction
XTAL system timing
generator
– 42 –
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling
digital filter
1 b i t D A C
L . P . F
C2F
DOUT