Yamaha 01x Service Manual page 25

YTS440B-F (X3009B00) mLAN-PH2 (mLAN
PIN
NAME I/O
NO.
1 IRERRN I Isochronous packet error flag input (Low active)
2 IRCVN I Isochronous reception enable input (Low active)
3 IRXN I Isochronous reception data enable input (Low active)
4 VDD - +3.3 V
5 VSS - Ground
6 ICLK I Isochronous master clock input (24.576MHz)
7 CYCLEOUT I Isochronous cycle out signal input
8 ICS I Isochronous cycle start signal input
9 CT I Isochronous cycle timer enable input
10 ITXN I Isochronous transmission data enable input (Low active)
11 VDD I +3.3 V
12 VSS I Ground
13 NC -
14 NC -
15 SCANE I Input for LSI test (usually connected to ground)
16 TSTI0 I
17 TSTI1 I
Input for LSI test (usually connected to ground)
18 TSTI2 I
19 TSTI3 I
20 VSS - Ground
21 ITREQN OD Isochronous transmission request output (Low active)
22 VDD - +3.3 V
23 IEOPN OD
Isochronous transmission packet test data signal output (Low active)
24 NC -
25 NC -
26 NC -
27 VSS - Ground
28 IDATA0 I/O
Isochronous data input/output
29 IDATA1 I/O
30 NC -
31 NC -
32 IDATA2 I/O Isochronous data input/output
33 VDD - +3.3 V
34 IDATA3 I/O
35 IDATA4 I/O Isochronous data input/output
36 IDATA5 I/O
37 VSS - Ground
38 NC -
39 IDATA6 I/O
Isochronous data input/output
40 IDATA7 I/O
41 NC -
42 IDATA8 I/O Isochronous data input/output
43 VDD - +3.3 V
44 IDATA9 I/O
45 IDATA10 I/O Isochronous data input/output
46 IDATA11 I/O
47 VSS - Ground
48 IDATA12 I/O
49 IDATA13 I/O Isochronous data input/output
50 IDATA14 I/O
51 VDD - +3.3 V
52 IDATA15 I/O Isochronous data input/output
53 SEQO O Loop connection output when 2 to 4 chips are used simultaneously
54 DBC O DBC timing output
55 VSS - Ground
56 LOCKN O PLL lock flag output (Low active)
57 PCA O Output for PLL external phase comaparator
58 PCB O Output for PLL external phase comaparator
59 VDD - +3.3 V
60 TSTI4 I
61 TSTI5 I
Input for LSI test (usually connected to ground)
62 TSTI6 I
63 TSTI7 I
64 NC -
65 TXE I/O Enable output (for master), input (for slave) for multi-chip transmission
66 VDD - +3.3 V
67 NC -
68 VSS - Ground
69 VCOCLK I PLL external VCO clock input
VCO frequency setting input
70 SVCO0 I
71 SVCO1 I VCO frequency setting input
72 SMCK0 I MCKO clock division rate setting input
73 NC -
74 NC -
75 SMCK1 I MCKO clock division rate setting input
76 SLV I 0: Master, 1: Slave when 2 to 4 chips are used simultaneously
77 SEQI I Loop connection input when 2 to 4 chips are used simultaneously
78 VDD - +3.3 V
79 NC -
80 NC -
81 VSS - Ground
82 ECKI I Bit clock inout for receptin from outside (128Fs or 256Fs)
83 EWCKI I Word clock input for reception from output (Fs)
84 PAR I Selection of serial, parallel input/output, 0: Serial, 1: Parallel
85 PDIR I Parallel data direction input, 0: Input, 1: Output
86 PDE I Parallel data enable input
87 BCK128I I Bit clock input for digital audio input (128Fs)
88 BCKI I Bit clock input for digital audio input (32Fs to 128Fs)
89 NC -
90 WCKI I Word clock input for digitral audio input (Fs)
91 VDD - +3.3 V
92 VSS - Ground
93 SWCK I/O Word clock output (for master), input (for slave) for multi-chip transmission
94 TSTI8 I
95 TSTI9 I
Input for LSI test (usually connected to ground)
96 TSTI10 I
97 TSTI11 I
98 VSS - Ground
99 NC -
100 WCKOD O Delay output of WCKO (Fs)
101 WCKO O Word clock output for digital audio output (Fs)
102 BCKO O Bit clock output for digital audio output (64Fs)
103 VDD - +3.3 V
104 NC -
TM
PIN
FUNCTION
NO.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Packet Handler 2)
NAME I/O
BCK128O O Bit clock output for digital audio output (128Fs)
MCKO O Master clock output for digital audio output (64Fs to 384Fs)
VSS - Ground
ECKO O Bit clock output for reception to outside (128Fs or 256Fs)
EWCKO O Word clock output for reception to outside (Fs)
VDD - +3.3 V
PCLK O Parallel data transfer clock output (128Fs or 256Fs)
VSS - Ground
NC -
PDIO0 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
NC -
PDIO1 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
VDD - +3.3 V
PDIO2 I/O
PDIO3 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
PDIO4 I/O
VSS - Ground
PDIO5 I/O
PDIO6 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
PDIO7 I/O
NC -
VDD - +3.3 V
NC -
NC -
VDD - +3.3 V
VSS - Ground
NC -
VDD - 3.3 V
NC -
PDIO8 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
PDIO9 I/O
NC -
PDIO10 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
VSS -
PDIO11 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
PDIO12 I/O
NC -
PDIO13 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
VDD - +3.3 V
PDIO14 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
NC -
PDIO15 I/O
Digital audio output (when PAR is "0") or parallel data bus (lower 16 bits) (when PAR is "1")
PDIO16 I/O
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
VSS - Ground
PDIO17 I/O
PDIO18 I/O
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
PDIO19 I/O
VDD - +3.3 V
PDIO20 I/O
PDIO21 I/O
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
PDIO22 I/O
VSS - Ground
PDIO23 I/O
PDIO24 I/O
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
PDIO25 I/O
VDD - +3.3 V
PDIO26 I/O
PDIO27 I/O
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
PDIO28 I/O
VSS - Ground
PDIO29 I/O
PDIO30 I/O
Digital audio input (when PAR is "0") or parallel data bus (upper 16 bits) (when PAR is "1")
PDIO31 I/O
VDD - 3.3 V
HD0 I/O
Data input/output
HD1 I/O
NC -
NC -
HD2 I/O Data input/output
VSS - Ground
HD3 I/O
HD4 I/O Data input/output
HD5 I/O
VDD - +3.3 V
HD6 I/O Data input/output
NC -
NC -
HD7 I/O Data input/output
IRQN OD Interrupt request output (Low active)
VSS - Ground
NC -
TSTI12 I
Input for LSI test (usually connected to ground)
TSTI13 I
NC -
TSTI14 I Input for LSI test (usually connected to ground)
VDD - +3.3 V
VSS - Ground
HA0 I Address input
HA1 I Address input
HA2 I Address input
HA3 I Address input
HA4 I Address input
HA5 I Address input
HA6 I Address input
HA7 I Address input
HA8 I Address input
VDD - +3.3 V
VSS - Ground
NC -
ICN I Initial clear input (Low active)
CSN I Chip select input (Low active)
WRN I Write enable input (Low active)
NC -
RDN I Read enable input (Low active)
O1X
MLN2: IC007
FUNCTION
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