Sony KP-43T70 Service Manual page 54

BLOCK DIAGRAM (3)
IC804
PEAK HOLD
5 Q804
7
6
IC802
IV CONV
CN3001 CN802 3
1
3 Q803
1
1 SENSOR LEFT 1
2
2
5
7
UPPER 3
6
10
8
LOWER 5
9
12
14 12
14 Q802
RIGHT 7
13
13
10
8 Q805
9
– 59 –
IC806
BUFF
6 39
7
18
5 17
16
15
57
3 I HP
7
1
I DREG OVF 26
2 I DREG BSY
27
I DREG ACK 28
8
SW SCL
50 49
Q801
SDA 48 47
10
8
46
6 58
9
61
62
59
55
12
14
13
44
9
12
X801
12MHz
11
36
32
33
34
35
37
IC808
(2/6) (5/6, 6/6)
4 3 10
TO A BOARD
VIDEO
BLOCK
TO A BOARD
SYSTEM CONTROL
BLOCK
– 60 –
12 15
11
3 4
13
6
12 5 30
IC808
(1/6, 3/6)
6
1
17
8
11 46
12 60
29 28
18
14
26
13
IC801
27
10
9
2
3
45
59
7 6 5
8 5 4
1
2
3
44
4 58
RJERST
1
RE-YM RE-R 3
YM OR R OR
Q806 Q807 2
21
4
IC808 RE-G 6
G OR
Q809 5
Q811 22
13
ATT 13
RE-B
B OR 11
Q808 12
23 38
Q812
ATT
9
RE-YS 8
YS OR
10
25
Q813
– 61 –
9
10
D+5V 8
14 6
15 11
16
13
9 8
4
6
5
15
11
16
13
14 6
15 11
16
13
14
15 6
16 11
13
2
REGI OUT 1
+5V
3
A
(4/4) (PJED-CPU, REGI CORRECTON)
1
L
TO G
BOARD
CN1502
DF
3
2
7
10
9
3
7 M
5
3 TO G
1 BOARD
CN651
2
7
3
VP N
4
TO G
BOARD
CN501
2
7
3
2
7
3
2
7
3
2
7
3
KP-48-53-61V80 -BD-6-M
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