Post Codes Tables; Chipset Post Codes - Acer Aspire 6930G Series Service Manual

POST Codes Tables

These tables describe the POST codes, drivers, and keys for the POST.

Chipset POST Codes

The following table details the Chipset POST codes and components used in the POST.
POST Code
0xA0 MRC Entry
0x01 Enable MCHBAR
0x02 Check ME existence
0x03 Check for DRAM initialization interrupt and reset fail
0x04 Determine the system Memory type based on first populated
socket
0x05 Verify all DIMMs are DDR2 and SO-DIMMS, which are
unbuffered
0x06 Verify all DIMMs are Non-ECC
0x07 Verify all DIMMs are single or double sided and not mixed
0x08 Verify all DIMMs are x8 or x16 width
0x09 Calculate number of Row and Column bits
0x10 Calculate number of banks for each DIMM
0x11 Determine raw card type
0x12 Find a common CAS latency between the DIMMS and the
MCH
0x13 Determine the memory frequency and CAS latency to program
0x14 Determine the smallest common timing value for all DIMMS
0x17 Power management resume
0x18 Program DRAM type (DDR2/DDR3) and Power up sequence
0x19 Program the correct system memory frequency
0x20 Program the correct Graphics memory frequency
0x21 Early DRC initialization
0x22 Program the DRAM Row Attributes and DRAM Row Boundary
registers PRE JEDEC.
0x23 Program the RCOMP SRAM registers
0x24 Program DRAM type (DDR2/DDR3) and Power up sequence
0x25 Program the DRAM Timing
0x26 Program the DRAM Bank Architecture register
0x27 Enable all clocks on populated rows
0x28 Program MCH ODT
0x29 Program tRD
0x30 Miscellaneous Pre JEDEC steps
0x31 Program clock crossing registers
0x32 Program the Egress port timings
0x33 Program the Memory IO registers
0x34 Perform steps required before JEDEC
0x35 Perform JEDEC memory initialization for all memory rows
Chapter 4
Function Phase Component
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