Read/Write Pca-A2 - HP 7936 Support Manual

current from input switches in the write chain,
applied across differential Read/Write Data lines
(OX, OY)
switch the current from a current source
in the write chain to the selected head. The write
current line is labeled Write Current (WC). Head
voltage swings, generated by the switching of the
write current through the inductive head are
monitored by a head transition detect circuit in the
IC. Absence of proper voltage swings, caused by an
open or short In either half of a head winding or
the absence of write current, will cause a current
to flow into the Unsafe output line
(US).
This line
is connected to the unsafe detector in read/write
PCA-A2, which in turn reports the fact to the
read/write controller via Current Unsafe
(CURUS-H).
When the IC is in the read mode, data is read from
the selected head, amplified, and output on the
differential
OX, OY
lines to a filter and amplifier
stage at the input of the read chain in read/write
PCA-A2. The same signal is also input to the
sampled servo switch in PCA-A2. If a fault condi-
tion exists such that write current is applied to the
IC when it is in the read mode, the write current
will be drawn from the Unsafe line and the fault
will be detected by the unsafe detector in
read/write PCA-A2 and reported to the read/write
controller.
5-91. READ/WRITE PCA-A2
The read/write system circuits contained in
PCA-A2 include a custom-designed read/write con-
troller IC, a
ht~ad
select encoder, a write chain, a
read chain, and amplifiers for the sampled and
dedicated servo code. Details of these circuits are
provided in
tl1t:~
following paragraphs.
5-92. READ/WRITE CONTROLLER IC. The
read/write controller IC is a custom-designed gate
array IC which operates with associated read chain
and write chain electronics to control the task of
reading from or writing to the data surfaces.
The controller consists of two independent sec-
tions - a control section and an encoder/decoder
section. The control section receives commands
and exchanges status information with the micro-
processor in controller PCA-A6 over the Data Path
Control Bus. The encoder/decoder section
Functional Description
7936 and 7937
exchanges disc data with the DMA/ECC
electronics in PCA-A6 via the Disc Data Bus,
receives timing information from the servo system,
and interfaces with the read chain and write chain
circuitry external to the IC.
5-93. Interface Signals. The signals which the
read/write controller exchanges with the micro-
processor in controller PCA-A6 are detailed below.
DATA PATH CONTROL BUS
OPCO-OPC7
OPRHW-L
OPAO-H
OPCS-L
OPIRQ-L
Data Path Control Bus
Data Path Read High, Write Low
Data Path Address Zero
Data Path Control Select
Data Path Interrupt Request
Commands and status information exchanged be-
tween the microprocessor in PCA-A6 and the
read/write controller via the Data Path Control
Bus are stored in three registers in the control sec-
tion: an address register (read/write only), a com-
mand register (write only), and a status register
(read only). The bus signals operate as follows:
Data Path Control Bus (OPCO-OPC7) is an 8-bit
bidirectional bus interconnecting the read/write
controller and the microprocessor in controller
PCA-A6. Transactions can take place at any time
provided that the setup and hold times around
Start of Sector (SOS-L) are not violated.
Data Path Read High/Write Low
(OPRHW-L)
when high enables the address or command register
to accept data. When low, OPRHW-L enables the
status or address registers to be read.
Data Path Address Zero
(OPAO-H)
when low
selects the control or status registers. When high,
OPAO-H
selects the address register.
During a microprocessor read, a low Data Path
Control Select (OPCS-L) enables the read/write
controller output buffers; and a high
OPCS-L
tristates the output buffers. During a microproces-
sor write, data is strobed into the internal registers
by the rising edge.
Data Path Interrupt Request
(OPIRQ-L),
when as-
serted, interrupts the microprocessor on a
read/write fault condition.
OPIRQ-L
will be
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