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MNEMONIC
SP~S
SPR-L
SRD-L
SRTF-H
SRVER-L
Functional Description
7936 and 7937
Ta ble 5-1. List of Mnemonics (18 of 23)
SIGNAL
Sampled
Servo
Position
Error*
Servo
Processor
Reset
Servo Read
Servo
Timing
Fault*
Servo Error*
SOURCE
IlA1
Ii]
A6
(IIA1
(IIA1
(II A1
DESCRIPTION
Sampled servo POSITION DEMODULATOR
output to SAMPLED/DEDICATED SELECT
SW.
SP~S
represents odd sampled servo
code dibits minus even sampled servo code
dibits. Signal is used for track following.
SP~S
can be monitored at pin 37 of the ser-
vo test point PCA.
Servo Control Bus signal from controller
PCA-A6 which resets the servo system.
SPR-L
is
connected
to
the
SERVO
CONTROLLER and the SERVO POWER
AMPLIFIER in servo PCA-AI via read/write
PCA-A2.
SERVO CONTROLLER Servo Control Bus
handshake
line
to
SERVO
CONTROL
INTERFACE in controller PCA-A6.
When
active,
SRD-L
enables controller PCA-A6 to
drive the bus with a byte of command
information.
SRD-L
is connected to controller PCA-A6 via
read/write PCA-A2.
FAULT
LATCHES
output
to
SERVO
CONTROLLER.
SRFT -H
is a combination of
Timing Errors
TERR1
and
TERR2.
SRTF-H
can be monitored at pin 49 of the
servo test point PCA.
FA UL T LATCHES output to read/write con-
troller.
SRVER-L
is a combination of off-
track or timing errors.
SRVER-L
can be monitored at pin 29 of the
servo test point PCA.
SRVER·L
is connected to the READ/WRITE
CONTROLLER in read/write PCA-AI. See
figure
IDII.
5-65
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