LG 84LA980V Service Manual page 71

Clock for URSA7
8pF
C1903
8pF
C1904
SPI Flash URSA7
SPI_CZ
R1904 33
SPI_DO
FLASH_WP
R1939 0
FLASH_WP_U
OPT
I2C EEPROM
+3.3V
URSA7 EEPROM
IC2007
R1EX24256BSAS0A
A0 VCC
1 8
A1 WP
2 7
A2 SCL
3 6
VSS SDA
4 5
I2CM_SCL_EEPROM
I2CM_SDA_EEPROM
Chip Config
Debug/ISP ADDR
Slabe (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3'd7:111:boot from SPI Flash
+3.3V
OPT 10K
R1908
10K
R1902
OPT 10K
10K R1907
R1901
OPT 10K
R1906
10K
R1900
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
XIN_URSA
XO_URSA
+3.3V
IC1901
MX25L3206EM2I-12G
C1901
0.1uF
16V
CS# VCC
1 8
SO/SIO1 HOLD#
2 7
R1905 10K
WP# SCLK
SPI_CK
3 6
GND SI/SIO0
SPI_DI
4 5
4MByte
C1900
0.1uF
25V
I2CM_SCL_EEPROM
I2CM_SDA_EEPROM
R1913
33
I2CM_SCL_URSA
R1911 33 OPT
I2CM_SCL1_URSA
R1916 33 URSA7 EEPROM
I2CM_SCL_M_Port
R1915 33
I2CM_SDA_URSA
R1912 33 OPT
I2CM_SDA1_URSA
R1914 33 URSA7 EEPROM
I2CM_SDA_M_Port
DIM0
DIM1
DIM2
URSA7 Reset
+3.3V
SW1901
JTP-1127WEM
1 2 OPT
C1902
22uF
3 4 10V
URSA7_Reset
0
R1924
Debugging for URSA7
I2C_S Port
URSA_DEBUG
P1905
12507WS-04L
WAFER-STRAIGHT
SW1902
1
JS2235S
2
SCL_M1_A 1 6 SDA_M1_A
R1958 R1959
R1922 33 0
3 SCL2_+3.3V_DB 0
URSA_MP
URSA_DEBUG URSA_MP 2 5
I2CS_SCL
R1921 R1960 URSA_DEBUG R1961
33 0 0
4 SDA2_+3.3V_DB
OPT OPT
URSA_DEBUG 3 4
SDA2_+3.3V_DB
SCL2_+3.3V_DB
5
I2C_M Port
URSA7 EEPROM
P1908
12507WS-04L
WAFER-STRAIGHT
1
2
3
I2CM_SCL_M_Port
4
I2CM_SDA_M_Port
5
AA28
URSA7_Reset RESET
AM3
XIN_URSA
XTALO
AL3
XO_URSA XTALI
AJ22
R1963 33
I2CS_SDA
I2CS_SDA
R1964 33 AH23
I2CS_SCL
I2CS_SCL
AG24
I2CM_SDA_URSA I2CM_SDA
AG25
I2CM_SCL_URSA
I2CM_SCL/VSYNC_LIKE1
R1929 33 E8
UART2_TX GPIO[0]/UART2_TX
UART2_TX
D8
R1927 33
UART2_RX GPIO[1]/UART2_RX
UART2_RX
R1928 33 D9
UART1_TX UART1_TX GPIO[2]/UART1_TX
R1926 33 E9
UART1_RX UART1_RX GPIO[3]/UART1_RX
AE31
SPI_CZ SPI_CZ
R1919 33 AD30
SPI_CK
SPI_CK
R1920 33 AD32
SPI_DI
SPI_DI
AE32
SPI_DO
SPI_DO
AB29
R1930 0
URSA7_stable
INT_R21/GPIO[41]
AA29
OPT R1933 33
INT_R20/GPIO[42]
AH25
OPT R1931 33
GPIO[10]/PWM_DIM_IN[0]
33 AG26
OPT R1932
GPIO[11]/PWM_DIM_IN[1]
F8
OPT R1934 33
IRE
AA26
TESTPIN
AA27
GND_EFUSE
I2CS_SDA
AH28
AH29
AJ27
AJ28
AH32
AH31
AG32
AG30
AF30
AG31
AE30
AF31
AH26
AH27
AJ25
AJ26
AL31
AM31
AK31
AL32
AJ30
AK32
AH30
AJ31
IC2500
LGE7410
AH24
VSYNC_LIKE2
AJ24
VSYNC_LIKE3
AE28
SPI1_CK/PWM2/GPIO58
AE29
SPI1_DI/PWM3/GPIO59
AF28
SPI2_CK/PWM0/GPIO56
AE27
SPI2_DI/PWM1/GPIO57
AG29
SPI3_CK/DIM10/GPIO54
AF27
SPI3_DI/DIM11/GPIO55
R1944 33
AG27
L_DIM_EN
SPI4_CK/DIM8/GPIO52
AG28
SPI4_DI/DIM9/GPIO53
AD27
VSYNC_LIKE/PWM5/GPIO40
AH20
DIM0/GPIO[32] DIM0
AG20
DIM1
DIM1/GPIO[33]
AJ21
DIM2/GPIO[34] DIM2
AH21
R1945
33 OPT
DIM3/GPIO[35]
AG21
R1950 33 OPT
DIM4/GPIO[36]
AG22 R1940
33 OPT
DIM5/GPIO[37]
AH22 R1935
33 OPT
DIM6/GPIO[38]
AG23
R1951
33 OPT
DIM7/GPIO[39]
E7
NC_21
F7
NC_22
D6
NC_23
D5
NC_24
E6
NC_25
E5
NC_26
F6
NC_27
F5
NC_28
AF4
VX1T_HTPDN
AE4
VX1T_LOCKN
AF5
R1936 0
I2CM_SDA1 I2CM_SDA1_URSA
AG4
R1946 0
I2CM_SCL1_URSA
I2CM_SCL1
AG5 R1941 33 OPT
TGPIO12
AH4
R1937 0
3D_FLAG
AH5
R1942 33 OPT
TGPIO14
AJ5
FLASH_WP_U
TGPIO15
IC2500
LGE7410
GPIO[8]/HDMIRX_CEC
GPIO[9]/HDMIRX_HPD
GPIO[6]/DDCDA_CK
GPIO[7]/DDCDA_DA
HDMI_RXCP
HDMI_RXCN
HDMI_RX0P
HDMI_RX0N
HDMI_RX1P
HDMI_RX1N
HDMI_RX2P
HDMI_RX2N
GPIO[4]/HDMITX_CEC
GPIO[5]/HDMITX_HPD
HDMITX_SCL
HDMITX_SDA
HDMITX_CLKP
HDMITX_CLKN
HDMI_TX0P
HDMI_TX0N
HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N
2013.03.18
EAX65309301
U_UART,GPIO 20 22
LGE Internal Use Only