Led 0 And 2 Configuration Defaults (Word 18H); Led Modes - Intel 8 LAN Information Manual

Table 16.

LED Modes

Mode (Bits
3:0)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
1.4.20

LED 0 and 2 Configuration Defaults (Word 18h)

This NVM word specifies the hardware defaults for the LEDCTL register fields controlling
the LED0 (LINK/ACTIVITY) and LED2 (LINK_100) output behaviors.
Table 17.

LED 0 and 2 Configuration Defaults (Word 18h)

Bit
15 LED2 Blink
14 LED2 Invert
13 LED2 Blink Mode
12 Reserved
11:8 LED2 Mode
16
Selected Mode
LINK_10/1000
LINK_100/1000
LINK-UP
FILTER_ACTIVITY
LINK/ACTIVITY
LINK_10
LINK_100
LINK_1000
Reserved
FULL_DUPLEX
COLLISION
ACTIVITY
BUS_SIZE
PAUSED
LED_ON
LED_OFF
Name Default
This bit indicates the initial value of the LED2_BLINK field.
0b 0b = LED2 is non-blinking.
1b = LED2 is blinking.
This bit indicates the initial value of the LED2_IVRT field.
0b 0b = LED2 has an active low output.
1b = LED2 has an active high output.
This bit defines the LED2 blink mode:
0b = Blink at 200 ms on and 200 ms off.
0b
1b = Blink at 83 ms on and 83 ms off.
Note: This field should be identical to the LED0 Blink Mode.
0b This bit is reserved and should be set to 0b.
These bits represent the initial value of the LED2_MODE field,
which specifies the event, state, or pattern displayed on LED2
0110b
(LINK_100) output. A value of 0110b causes this to indicate
100 Mb/s operation.
Source Indication
Asserted when either 10 Mb/s or 1000 Mb/s link is established
and maintained.
Asserted when either 100 Mb/s or 1000 Mb/s link is
established and maintained.
Asserted when any speed link is established and maintained.
Asserted when link is established and packets are being
transmitted or received that passed MAC filtering.
Asserted when link is established and when there is no
transmit or receive activity.
Asserted when a 10 Mb/s link is established and maintained.
Asserted when a 100 Mb/s link is established and maintained.
Asserted when a 1000 Mb/s link is established and maintained.
Reserved.
Asserted when the link is configured for full duplex operation.
Asserted when a collision is observed.
Asserted when link is established and packets are being
transmitted or received.
Asserted when the MAC detects a 1-lane PCIe* connection.
Asserted when the MAC transmitter is flow controlled.
Always asserted.
Always de-asserted.
Description
NVM Information Guide—ICH8