Block Diagrams - Philips CDR570 Service Manual

Block diagrams

6. Block diagrams
CDR MAIN BOARD BLOCK DIAGRAM
CDL4009
LOADER ASSY
FORWARD SENSE CIRCUIT
7119, 7120
CDM3800
TURN
1330
TABLE FSON
FSOF
M
EFMTIM3
LO9805
EPONRC
WPONRC
LDON
BIASC
ERON
RECORDING
1000 CDRW
ALS
ASTROBE
FSA
AINTON
I-ERASE
IE
EPONRC
I-WRITE
IW
WPONRC
LDON
I-READ
IR BIASC
RECORDING
CDRW
MODULATOR PW
FS LASER
+
DALPHA
FS30V
PDAR
ERON
+
CAHF TO CDR60 RECORDING
(HF DATA CAPTURE)
PHOTO
DIODES
AEGER
B1 TZA1020
B2
RECORDING
DIODE
C3 C4
C1LF - C4LF
STAGE
C1 C2
2
A1LF, A2LF
DIODE
B1LF, B2LF
A1 A2
STAGE
1 ERON
S2V9
GAP
REF
RAD+, RAD-
RADIAL
FOC+, FOC-
RECORDING
FOCUS
PCS PRE-AMP
SLEDGE 1220
SIN+, SIN- NE532D
COS+, COS-
M
SL+, SL-
POWER
DRIVER
BA5938FM
TRAY
M
1200
TR+, TR-
TRAY
TRAYSW
SWITCH
CDR 3rd gen.
7330
HALL
UCOIL, VCOIL, WCOIL, U+, U-, V+, V-, W+, W-, HALL+, HALL-
MOTOR
DRIVER
7126C 7050A, 7050B
BA6856FP
FSW
7126D
FSR
TO MACE2 (PCS)
7008
RDGAIN FSCLR FSWS FSRS
LWRT
LWRT
POR E5V
TIMING
I / O
SHIFT N EFMDATA, EFMCLK
N-1, N+1
REG
I2C
DP4 ERASEC PERASE PWRITE
7016
XDAC
M62364
PWD
DAC DAC
PWB
DAC
PWD
PWD
DAC
DELTAP
LASDACDI
S2V9
12
DAC LASDACCK
PRCOARSE
BIT LASDACLD
PRFINE SHIFT
S2V9
DAC REGISTER
PWB
S2V9
DAC
PWMIN
P
MIN/MAX
S2V9
CONTR DAC
PWMAX
I
ALS
ASTROBE
AINTON
OFFTRACK
DALPHA
7010
LLP
I2C
ATIPSYNC
ALPHA
ALPHA0
PW
DETECTOR
BETA
A1, A2, CALF
DETECTOR
OPC
7050C
S2V9
WOBBLE
BALANCE
TLN, MIRN LASER
NORMA-
FEN, REN CONTROL
LIZER
+ / -
RE
I V
7215A
TRACK
7225 FTCH, FTCL
COUNTER
FROM FORWARD
SENSE CIRCUIT
FSR, FSW
PCS
REFSIN, SINPHI, REFCOS, COSPHI
7240
RAD
FOCUS VRA, VFO, VSL SERVO
CONTROLS
SLEDGE
TRAY TRAYIN, TRAYOUT
PORT 5
TRAYSWF
PORT 4
6. GB 33
HALL U, HALL V, HALL W
MOTO1
7300
ADDRESS
BUS
CDR60
SAA7392
SYST CLK
GENERATOR
MOTOR/TACHO
OFFTRACK
INTERFACE
CDR60PLL
FROM MACE2
CDR60LWRT
MODULATOR
CONTROL
LLP
DECODER
EBU
ENCODER
EFM
EFMDATA
DOBM-CDR
MODULATOR
ERROR
I 2 S I 2 S BUS
EFM CLOCK
EFMCLK
CORRECTION
GENERATOR I / O
AND MEMORY
PROCESSOR
ATIPSYNC
WOBBLE
SUB-
SUBCODE BUS
PROCESSOR
WOBBLE
CODE
I / O
CD TEXT
BIT
DEMODULATOR
DETECTOR
HF DATA SUB - CPU INTERFACE
RESET
CAPTURE
HIN SRSTN CDR60CS MRDN
MWRN
ALE
7360
HFS0
HF AMP
FILTER
CAHF
FROM CDM3800
(PDAR)
7207
2
I 2 C
C BUS
EEPROM
M24C08
DATA
BUS
CDR60INT
7270
PORT
MUTE, ATT, DEEMP
REGISTERS
BE-RESET
I 2 S1-MS
8051
DSA-CDR
CPU
CDR60PLL
TO CDR60
RAM ROM
SPECIAL FUNCTION
REGISTERS
7802
FLASH
RAM
EPROM
MACE2
SAA7399
ADC
CLOCK
AGC TEST DEBUG
GEN
REF
D3V3
+5VA
7703 D5V
D5VS
FLASH
L5V
ROM
L-5V
POWER
-8VA
PART
DATA
A-8V
BUS
+9SRVPWR
7702
+12VA
DRAM
L12V
P12V
12VPWR
FS30V
D3V3
7701
A1 - A20 D16 - D31
7704
EBU-IN1
RESET
D3V3
MC33464
MASTER
I 2 S1
RESET
7710
RESET
D5V
MC33464
SYS-RESET
I 2 C BUS
INT-COPY-ANA
NOT FOR CDR950/951
7801
7401
DIGITAL
POT
DS1807
NOT FOR CDR570/930
SEL-HP-OUT
DASP
MCF5244 7407
7405
ANA-OUT
DIGITAL AUDIO
SIGNAL
ANALOG
PROCESSOR CD-ANA-OUT
IN
7406
NMUTE
7409
SYS-CLK-11W CODEC
ANALOG
UDA1341TS
OUT
I 2 S BUS
I 2 S2 / I 2 S4
ADC / DAC
L3 BUS
EXT-DIG-IN
EBU-IN2
DIG-OUT-C
EBU-OUT1
EXT-OPT-IN
EBU-IN3
CDR775 ONLY
SYS-RESET
DSA-CD
I 2 S BUS-CD
I 2 S3
DOBM-CD
EBU-IN4
SYS-CLK-16W (16.9344 Mhz)
XTRIM
1707
33.8688 MHz
7208 7209
7706A
DEMUX
/2
74F74D
ADDRESS
SYS-CLK-BE
BUS
(8.4672 Mhz)
1500
+5V
-8V
+12V
VDC2, VDC1, VFTD
F934
D5V
EXT-ANA-IN
CD-ANA-OUT
1410
7408
1400
1708
SYS-CLK-8W (8.4672 Mhz)
CL06532018_025.eps
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