Philips CDR570 Service Manual page 21

Service modes, repair tips and faultfinding trees CDR 3rd gen. 5. GB 21
Reset & Clock
Master reset.
Since the Mainboard is more or less mix-mode between +3V3
and +5V devices, special treatment for the RESET behavior is
wishful. Controlling the RESET only from 1 power supply could
lead to collisions between different devices, damaging the
internal I/O structure of the devices. To avoid this the +3V3 and
the +5V are guarded by a special device. These devices keep
the output low as long as the power supply is not stable or is
not above the required level. As soon as the power supply is
stable it switches the output to "HIGH-Z". The output is an open
collector type. From then onwards the line can be controlled by
means of external pull-up resistors. Benefit of the open-
collector devices is that several of those devices can be tight
together at the outputs. In our case we used a device on the
+5V and one on the +3V3. This means that both power supplies
need to be stable before the RESET of the Master processor is
released.
Resetting several processors in the same structure by means
of the power supplies invokes certain risks. The duration of
initialization after reset is processor and Code depending. It
can lead to hang-up in those cases that communication
between the processors is "time" driven. Meaning that only in a
certain time frame the establishment of the communication-bus
must take place. If not successful the Bus hangs!
To avoid these kinds of problems, only 1 RESET is depending
on the power supply, and this is the RESET of the Master
controller. The same master controller will then take care of the
RESET of the other devices. In the next figure this is explained.
+3V3
+3V3
MC33464 Basic Engine
+3V3
MACE
3V0
MASTER
DASP
Display
+5V
MC33464
+5V
4V7
CD loader
80C52 alike
AM29LV800BB
CL06532018-014.eps
230200
Figure 5-12
For further measurings see next reset and clock flowcharts.