Receiver - JBL JSR-400 Service Manual

Dolby Pro-Logic A/V Receiver
Ò
SYC
XIN
XOUT
FMIN
AMIN
Terminal Description
Pin No. Terminal
1 XOUT
2
XIN
3 CE
4 5CL
5 DATA
6 SYN
7
AUTO/MONO
8 FM
9
AM
10 AMIN
11 FMIN
V
12
DD
V
13
DD
14
PD1
15 PD2
V
16
SS
INTEGRATED CIRCUIT DIAGRAMS 2
Tuner PCB IC2 - (LM7001)
(PLL Synthesizer and Controller)
6
2
1
11
11
3
CE CL DATA
Connect to the 7.2 Mhz crystal oscillator.
Chip enable terminal. Connect to the PLL terminal of microprocessor.
Serial clock input terminal. Connect to the CLOCK terminal of microprocessor.
Serial data input. Connect to the DATA terminal of micro processor.
Not used
AUTO/MONO selection output terminal. "L" when FM.
FM band control output terminal. "L" when FM.
AM band control output terminal. "L" when AM.
AM local oscillator input terminal.
FM local oscillator terminal.
1
Power supply terminal for back-up.
2
Power supply terminal.
Charge pump output of the phase detector which constitues the PLL. High level is output when the divided
local oscillator frequency is higher than the reference frequency. In the opposite case, low level is output.
Floating occurs when the frequency matched. The output is applied to the variable capacitor diode in the
local oscillator through the low pass filters.
Ground terminal.
Phase Detector
Charge Pump
Reference Divider
Programable Divider
Shift Register - Latch
4 5 7
BO1
Description
14
PD1
15
PD2
12
VDD1
13
VDD2
12 6
VSS
8 9
BO2 BO3
JSR-400
3 7