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Appendix
7-3 Block Diagram Example
(1) CLT-1583
+12V
Tuner Board
+9V
Sub CPU
M37272M6
U101
IIC
+CONTROL
TU201
Tuner / IF
TMQJ8
17
7
6
47
48 46
+9V
34
AV Switch U46
CXA2089Q
33
30
32
7
3
5
L
R
V
S
Monitor Output
AV1 Input
(2) CLT-2053
Tuner Board
Sub CPU
M37272M6
U101
IIC
+CONTROL
TU201
Tuner / IF
TMQJ8
17
7
6
47
48 46
+9V
34
AV Switch U46
33
30
32
7
3
V
L
R
S
Monitor Output
U45
R
Audio AMP
3
L
Headphone (J26)
4
LA4263
1
8
10
U44
8
23
16
Audio Processor
Main Board
NJW1138M
1
30
S_CLK / SIN_OUT/ ENABLE_IN / ENABLE_OUT
V33D
U19
CC_R
3
Video Decoder
VY [0-7]
CC_G
2
CC_B
VPC3230D
VUV [0-7]
1
72
74
71
5 4 6
41
39
40
43 45
18
16
1
2
4
8
9
11
L
R
L
R Y Cb Cr
V
V
Component
AV2 Input
U45
R
Audio AMP
3
+14V
L
4
LA4263
1
8
10
U44
8
23
+9V
16
Audio Processor
Main Board
NJW1138M
1
30
S_CLK / SIN_OUT/ ENABLE_IN / ENABLE_OUT
V33D
U19
CC_R
3
Video Decoder
CC_G
2
CC_B
VPC3230D
1
72
74
71
5
41
39
40
43 45
18
16
CXA2089Q
5
1
2
4
8
9
11
V
L
R
V
L
R
AV2 Input
AV1 Input
R
Speaker (R)
L
Speaker (L)
VCPU 33/18
U36
DRO [0-7]
Main Scaler / (Main)CPU
DGO [0-7]
PW113-10Q
DBO [0-7]
PIXELWORKS
MENORY
DATA
Flash ROM
8Mbits
V33D
U6
AVDD
Graphic A/D
PVDD
AD9883
R_PC
L_PC
54 30
48
31
43
R
G
B
H
V
D-SUB
PC Input
R
Headphone (J26)
L
VCPU 33/18
VY [0-7]
Main Scaler / (Main)CPU
PW113-10Q
VUV [0-7]
PIXELWORKS
4 6
U36
MENORY
DATA
Flash ROM
U30
8Mbits
L R
Y Cb Cr
Audio
Component
Board
AV3 Input
-30-
Training Manual Principle of LCD
LCD Panel
V33
IC1
LVDS
Interface
THC63LVDM83A
VCPU 33
37
U30
Fig. 33
Block Diagram: CLT-1583
Speaker (R)
Speaker (L)
DRO [0-7]
DGO [0-7]
LCD Panel
DBO [0-7]
VCPU 33
37
Fig. 34
Block Diagram: CLT-2053
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