Interrupt - IBM EM78P221/2N Specification

EM78P221/2N
8-Bit Microcontroller with OTP ROM

6.6 Interrupt

The EM78P221/2N has four interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt INT0, INT1
4. When the Comparator 1 output status changes
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV
R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes. Port 6
Input Status Change Interrupt will wake up the EM78P221/2N from sleep mode if it is
enabled prior to going into sleep mode by executing SLEP. When wake-up occurs, the
controller will continue to execute the succeeding program if the global interrupt is
disabled. If enabled, it will branch out to the interrupt vector 008H.
The external interrupt has a built-in digital noise rejection circuit (if the input pulse is
less than 8-system clock time, it is eliminated as noise. Edge selection is possible with
/INT. Refer to Word 1 Bits 8~7 (Section 6.13.2, Code Option Register (Word 1)) for
digital noise rejection definition.
During a power source unstable situation, like during external power noise interference
or EMS test condition, it will cause the power to vibrate fiercely. While Vdd is still
unsettled, the supply voltage may be below working voltage. When the system supply
voltage Vdd is below the working voltage, the IC kernel must automatically keep all
register status.
Bank 0-RE and Bank 0-RF are the interrupt status register that records the interrupt
requests in the relative flags/bits. Bank 1-RE and Bank 1-RF are interrupt mask
registers. The global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction
will be fetched from Address 008H. Once in the interrupt service routine, the source of an
interrupt can be determined by polling the flag bits in Bank 0-RE and Bank 0-RF. The
interrupt flag bit must be cleared by instructions before leaving the interrupt service
routine to avoid recursive interrupts.
When interrupt mask bits is "Enable", the flag in the Interrupt Status Register (RF) is set
regardless of the ENI execution. Note that the result of Bank 0-RE/RF will be the logic
AND of BANK 0-RE/RF and Bank 1-RE/RF (refer to Fig. 6-8). The RETI instruction
ends the interrupt routine and enables the global interrupt (the ENI execution).
When any interrupt occurs, the contents of ACC, R1 (Bits 5, 4, 1, 0), R3 (Bits 2 ~0), R4
registers are pushed to the corresponding stack (Fig 6-9). After the RETI instruction is
executed, the content of the corresponding stack are popped to ACC, R1 (Bits 5, 4, 1, 0),
R3 (Bits 2 ~0), R4 registers.
36 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)