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Elan EM78P259N/260N Product Specification

8-bit microprocessor with otp rom
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EM78P259N/260N
8-Bit Microprocessor
with OTP ROM
Product
Specification
D
. V
1.2
OC
ERSION
ELAN MICROELECTRONICS CORP.
May 2007

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Summary of Contents for Elan Elan EM78P259N/260N

  • Page 1 EM78P259N/260N 8-Bit Microprocessor with OTP ROM Product Specification ERSION ELAN MICROELECTRONICS CORP. May 2007...
  • Page 2 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo © 2005~2007 by ELAN Microelectronics Corporation Copyright All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification.

  • Page 3: Table Of Contents

    Contents General Description ... 1 Features ... 1 Pin Assignment ... 2 Block Diagram ... 2 Pin Description... 3 EM78P259NP/M... 3 EM78P260NP/M/KM ... 4 Function Description ... 5 Operational Registers... 5 6.1.1 R0 (Indirect Address Register) ...5 6.1.2 R1 (Time Clock /Counter)...5 6.1.3 R2 (Program Counter) and Stack ...5 6.1.3.1 Data Memory Configuration...7...
  • Page 4 Contents 6.2.13 IOC61 (TCCB Counter) ...23 6.2.14 IOC71 (TCCBH/MSB Counter)...24 6.2.15 IOC81 (TCCC Counter)...24 6.2.16 IOC91 (Low Time Register) ...25 6.2.17 IOCA1 (High Time Register)...25 6.2.18 IOCB1 High/Low Time Scale Control Register) ...25 6.2.19 IOCC1 (TCC Prescaler Counter)...26 TCC/WDT and Prescaler... 27 I/O Ports ...
  • Page 5 6.11 Oscillator ... 60 6.11.1 Oscillator Modes ...60 6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal) ...61 6.11.3 External RC Oscillator Mode ...62 6.11.4 Internal RC Oscillator Mode ...63 6.12 Power-on Considerations ... 64 6.12.1 Programmable WDT Time-out Period...64 6.12.2 External Power-on Reset Circuit ...64 6.12.3 Residual Voltage Protection ...65 6.13 Code Option ...
  • Page 6 Contents Specification Revision History Doc. Version Initial official version Added the IRC drift rate in the feature 1. Improved the contents and format of the Features section, Fig.4-1 EM78P259N/260N Functional Block Diagram, Fig.6-2 TCC and WDT Block Diagram and Fig.6-11 IR/PWM System Block Diagram. 2.

  • Page 7: General Description

    General Description The EM78P259N and EM78P260N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. The series has an on-chip 2K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s code. Three Code option words are also available to meet user’s requirements.

  • Page 8: Pin Assignment

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Pin Assignment (1) 18-Pin DIP/SOP P52/ADC2 P53/ADC3 P54/TCC/VREF /RESET P60//INT P61/TCCA P62/TCCB P63/TCCC Fig. 3-1 EM78P259NP/M Block Diagram Instruction Register Instruction Decoder R3 (Status Reg.) Fig. 4-1 EM78P259N/260N Functional Block Diagram 2 • (2) 20-Pin DIP/SOP/SSOP P51/ADC1 P52/ADC2 P50/ADC0...

  • Page 9: Pin Description

    Pin Description 5.1 EM78P259NP/M Symbol Pin No. Type P60~P67 6~13 P50~P55 16~18 CIN-, CIN+ 12, 11 OSCI OSCO /RESET 3, 7, TCC, TCCA, TCCB, TCCC 8, 9 1, 2, ADC0~ADC3 17, 18 IR OUT VREF /INT Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) 8-Bit Microprocessor with OTP ROM Function...

  • Page 10: Em78P260Np/M/Km

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 5.2 EM78P260NP/M/KM Symbol Pin No. Type P60~P67 7~14 P50~P57 17~20 CIN-, CIN+ 13, 12 OSCI OSCO /RESET 4, 8, TCC, TCCA, TCCB, TCCC 9, 10 2, 3, ADC0~ADC3 18, 19 IR OUT VREF /INT 4 •...

  • Page 11: Function Description

    Function Description 6.1 Operational Registers 6.1.1 R0 (Indirect Address Register) R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4). 6.1.2 R1 (Time Clock /Counter) Increased by an external signal edge which is defined by the TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock.
  • Page 12 EM78P259N/260N 8-Bit Microprocessor with OTP ROM "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack.

  • Page 13: Data Memory Configuration

    6.1.3.1 Data Memory Configuration Address R PAGE registers (Indirect Addressing Register) (Time Clock Counter) (Program Counter) (Status Register) (RAM Select Register) (Port 5) (Port 6) (Port 7) (ADC Input Select Register (ADC Control Register) (ADC Offset Calibration Register) (The converted value AD11~AD4 of ADC) (The converted value AD11~AD8 of ADC)

  • Page 14: R3 (Status Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.1.4 R3 (Status Register) Bit 7 Bit 6 IOCS Bit 7 (RST): Bit of reset type Set to “1” if wake-up from sleep on pin change, comparator status change, or AD conversion completed. Set to “0” if wake-up from other reset types Bit 6 (IOCS): Select the Segment of IO control register 0 = Segment 0 (IOC50 ~ IOCF0) selected...

  • Page 15: R5 ~ R6 (Port 5 ~ Port 6)

    6.1.6 R5 ~ R6 (Port 5 ~ Port 6) R5 & R6 are I/O registers The upper 2 bits of R5 are fixed to “0” (if EM78P259N is selected). Only the lower 6 bits of R5 are available (this applies to EM78P259N only as EM78P260N can use all the bits) 6.1.7 R7 (Port 7) EM78P259N/260N...

  • Page 16: R8 (Aisr: Adc Input Select Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 3 & Bit 2 (RCM1, RCM0): 6.1.8 R8 (AISR: ADC Input Select Register) The AISR register individually defines the pins of Port 5 as analog input or as digital I/O. Bit 7 Bit 6 –...

  • Page 17: R9 (Adcon: Adc Control Register)

    6.1.9 R9 (ADCON: ADC Control Register) Bit 7 Bit 6 VREFS CKR1 Bit 7 (VREFS): Input source of the Vref of the ADC The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P54/TCC/VREF must be “0.” The P54/TCC/VREF pin priority is as follows: Bit 6 &...

  • Page 18: Ra (Adoc: Adc Offset Calibration Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 1 ~ Bit 0 (ADIS1 ~ADIS0): Analog Input Select 6.1.10 RA (ADOC: ADC Offset Calibration Register) Bit 7 Bit 6 CALI SIGN Bit 7 (CALI): Bit 6 (SIGN): Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits Bit 2 ~ Bit 0: 6.1.11 RB (ADDATA: Converted Value of ADC) Bit 7...

  • Page 19: Rc (Addata1H: Converted Value Of Adc)

    6.1.12 RC (ADDATA1H: Converted Value of ADC) Bit 7 Bit 6 “0” “0” When AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set.

  • Page 20: Rf (Interrupt Status 2 Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 2 (CMPWE): Comparator wake-up enable bit Bit 1 (ICWE): Bit 0: 6.1.15 RF (Interrupt Status 2 Register) Bit 7 Bit 6 LPWTIF HPWTIF Note: “ 1 ” means with interrupt request RF can be cleared by instruction but cannot be set. IOCF0 is the relative interrupt mask register.

  • Page 21: Special Purpose Registers

    6.2 Special Purpose Registers 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 6.2.2 CONT (Control Register) Bit 7 Bit 6 INTE Note: The CONT register is both readable and writable Bit 6 is read only.

  • Page 22: Ioc50 ~ Ioc70 (I/O Port Control Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits PST2 Note: Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)] Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)] 6.2.3 IOC50 ~ IOC70 (I/O Port Control Register) "1"...

  • Page 23: Ioc90 (Tccb And Tccc Control Register)

    Bit 1 (TCCATS): Bit 0 (TCCATE): 6.2.5 IOC90 (TCCB and TCCC Control Register) Bit 7 Bit 6 TCCBHE TCCBEN Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of counter Bit 6 (TCCBEN): TCCB enable bit Bit 5 (TCCBTS) TCCB signal source Bit 4 (TCCBTE): TCCB signal edge Bit 3:...

  • Page 24: Ioca0 (Ir And Tccc Scale Control Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.6 IOCA0 (IR and TCCC Scale Control Register) Bit 7 Bit 6 TCCCSE TCCCS2 Bit 7 (TCCCSE): Scale enable bit for TCCC 18 • 0 = increment if the transition from low to high takes place on the TCCC pin 1 = increment if the transition from high to low takes place on the TCCC pin...
  • Page 25 Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits Bit 3 (IRE): Bit 2 (HF): Bit 1 (LGP): Bit 0 (IROUTE): Control bit to define the P67 (IROUT) pin function Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) 8-Bit Microprocessor with OTP ROM The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to determine the scale ratio of TCCC as shown below:...

  • Page 26: Iocb0 (Pull-Down Control Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.7 IOCB0 (Pull-down Control Register) Bit 7 Bit 6 /PD57 /PD56 Note: The IOCB0 register is both readable and writable Bit 7 (/PD57): Control bit used to enable the pull-down function of the P57 pin (applicable to EM78P260N only) 0 = Enable internal pull-down 1 = Disable internal pull-down...

  • Page 27: Iocd0 (Pull-High Control Register)

    6.2.9 IOCD0 (Pull-high Control Register) Bit 7 Bit 6 /PH57 /PH56 Note: The IOCD0 register is both readable and writable Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to EM78P260N only). 0 = Enable internal pull-high; 1 = Disable internal pull-high.

  • Page 28: Iocf0 (Interrupt Mask Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 5 (ADIE): ADIF interrupt enable bit 0 = disable ADIF interrupt 1 = enable ADIF interrupt Bit 4 (CMPIE): CMPIF interrupt enable bit. 0 = disable CMPIF interrupt 1 = enable CMPIF interrupt Bit 3 (PSWE): Prescaler enable bit for WDT 0 = prescaler disable bit, WDT rate is 1:1 1 = prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0...

  • Page 29: Ioc51 (Tcca Counter)

    Bit 5 (TCCCIE): TCCCIF interrupt enable bit Bit 4 (TCCBIE): TCCBIF interrupt enable bit Bit 3 (TCCAIE): TCCAIF interrupt enable bit Bit 2 (EXIE): Bit 1 (ICIE): Bit 0 (TCIE): 6.2.12 IOC51 (TCCA Counter) The IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any reset condition and is an Up Counter.

  • Page 30: Ioc71 (Tccbh/Msb Counter)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.14 IOC71 (TCCBH/MSB Counter) The IOC71 (TCCBH) is an 8-bit clock counter for the most significant byte of TCCBX (TCCBH). It can be read, written, and cleared on any reset condition. When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then TCCB is a 16-bit length counter.

  • Page 31: Ioc91 (Low Time Register)

    6.2.16 IOC91 (Low Time Register) The 8-bit Low time register controls the active or Low segment of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as follows: ■...

  • Page 32: Iocc1 (Tcc Prescaler Counter)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High time scale bits: HTS2 HTS1 Bit 3 (LTSE): Low time scale enable bit. 0 = scale disable bit, Low time rate is 1:1 1 = scale enable bit, Low time rate is set as Bit 2~Bit 0. Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low time scale bits: LTS2 6.2.19 IOCC1 (TCC Prescaler Counter)

  • Page 33: Tcc/Wdt And Prescaler

    6.3 TCC/WDT and Prescaler There are two 8-bit counters available as prescalers that can be extended to 16-bit counter for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PWR2 ~ PWR0 bits of the IOCE0 register are used to determine the WDT prescaler.

  • Page 34: I/O Ports

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 1CLK (Fosc/1) 2 CLK (Fosc/2) TCC Pin TE (CONT) 8-Bit counter 8 to 1 MUX WDTE (IOCE0) WDT Time out 6.4 I/O Ports The I/O registers (Port 5, Port 6, and Port 7) are bi-directional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software.
  • Page 35 PORT Note: Open-drain is not shown in the figure. Fig. 6-3 I/O Port and I/O Control Register Circuit for Port 6 and Port 7 PORT Bit 6 of IOCE Note: Open-drain is not shown in the figure. Fig. 6-4 I/O Port and I/O Control Register Circuit for P60 (/INT) Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) 8-Bit Microprocessor with OTP ROM...
  • Page 36 EM78P259N/260N 8-Bit Microprocessor with OTP ROM P50 ~ P57 PORT Note: Pull-high (down) is not shown in the figure. Fig. 6-5 I/O Port and I/O Control Register Circuit for Port 50 ~ P57 I O C F.1 T I 0 T I 1 T I 8 Fig.

  • Page 37: Usage Of Port 5 Input Change Wake-Up/Interrupt Function

    6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function (1) Wake-up (a) Before Sleep 1. Disable WDT 2. Read I/O Port 5 (MOV R5,R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction (b) After wake-up →...
  • Page 38 EM78P259N/260N 8-Bit Microprocessor with OTP ROM All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper 3 bits of R3 is cleared The IOCB0 register bits are set to all "1" The IOCC0 register bits are set to all "1"...
  • Page 39 Case [c] If Comparator output status change is used to wake-up the EM78P259N/ 260N and CMPWE bit of the RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P259N/260N can be awakened only with Case 4. Wake-up time is dependent on the oscillator mode. In RC mode the Wake-up time is 32 clocks (for stable oscillators).

  • Page 40: Wake-Up And Interrupt Modes Operation Summary

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.5.1.1 Wake-Up and Interrupt Modes Operation Summary All categories under Wake-up and Interrupt modes are summarized below. Signal Sleep Mode INT Pin RE (ICWE) Bit1=0, IOCF0 (ICIE) Bit1=0 Oscillator, TCC, TCCX and IR/PWM are stopped. Port5 input status changed wake-up is invalid.
  • Page 41 Signal RE (CMPWE) Bit2=0, IOCE0 (CMPIE) Bit4=0 Comparator output status changed wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (CMPWE) Bit2=0, IOCE0 (CMPIE) Bit4=1 Set RE (CMPIF)=1, Comparator output status changed wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. Comparator RE (CMPWE) Bit2=1, IOCE0 (CMPIE) Bit4=0 (Comparator Output...

  • Page 42: Register Initial Values After Reset

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.5.1.2 Register Initial Values after Reset The following summarizes the initialized values for registers. Address Name Reset Type Bit Name Type IOC50 Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on IOC60 /RESET and WDT Wake-up from Pin Change...
  • Page 43 Address Name Reset Type Bit Name Power-on IOCD0 /RESET and WDT (PHCR) Wake-up from Pin Change Bit Name Power-on IOCE0 /RESET and WDT Wake-up from Pin Change Bit Name Power-on IOCF0 /RESET and WDT Wake-up from Pin Change Bit Name Power-on IOC51 /RESET and WDT...
  • Page 44 EM78P259N/260N 8-Bit Microprocessor with OTP ROM Address Name Reset Type Bit Name Power-on IOCA1 /RESET and WDT (HTR) Wake-up from Pin Change Bit Name Power-on IOCB1 /RESET and WDT (HLTS) Wake-up from Pin Change Bit Name Power-on IOCC1 /RESET and WDT (TCCPC) Wake-up from Pin Change...
  • Page 45 Address Name Reset Type Bit Name Power-on 0x04 R4(RSR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x05 /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x06 /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin...

  • Page 46: Controller Reset Block Diagram

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Address Name Reset Type Bit Name Power-on /RESET and WDT (ADDATA1H) Wake-up from Pin Change Bit Name Power-on /RESET and WDT (ADDATA1L0) Wake-up from Pin Change Bit Name Power-un /RESET and WDT (ISR2) Wake-up from Pin Change Bit Name Power-on...

  • Page 47: The T And P Status Under Status (R3) Register

    6.5.2 The T and P Status under STATUS (R3) Register A reset condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled). The values of RST, T, and P as listed in the table below, are used to check how the processor wakes up.
  • Page 48 EM78P259N/260N 8-Bit Microprocessor with OTP ROM The external interrupt has an on-chip digital noise rejection circuit. Input pulse less than 8 system clock time is eliminated as noise. However, in Low Crystal oscillator (LXT) mode the noise rejection circuit is disabled. Edge selection is possible with INTE of CONT.
  • Page 49 /IRQn /RESET Interrupt sources ENI/ DISI In EM78P259N/260N, each individual interrupt source has its own interrupt vector as depicted in the table below. Interrupt Vector 003H 006H 009H 00CH 00FH 012H 015H 018H 01BH 01EH Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) 8-Bit Microprocessor with OTP ROM RFRD IOCFWR...

  • Page 50: Analog-To-Digital Converter (Adc)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.7 Analog-to-Digital Converter (ADC) The analog-to-digital circuitry consist of a 4-bit analog multiplexer; three control registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA/RB, ADDATA1H/RC, & ADDATA1L/RD), and an ADC with 12-bit resolution as shown in the functional block diagram below.

  • Page 51: R9 (Adcon: Ad Control Register)

    Bit 1 (ADE1): Bit 0 (ADE0): 6.7.1.2 R9 (ADCON: AD Control Register) Bit 7 Bit 6 VREFS CKR1 The ADCON register controls the operation of the AD conversion and determines which pin should be currently active. Bit 7(VREFS): Input source of the ADC Vref The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time.

  • Page 52: Ra (Adoc: Ad Offset Calibration Register)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 4 (ADRUN): ADC starts to RUN. Bit 3 (ADPD): Bit 2: Bit 1 ~ Bit 0 (ADIS1 ~ ADIS0): Analog Input Select 6.7.1.3 RA (ADOC: AD Offset Calibration Register) Bit 7 Bit 6 CALI SIGN Bit 7 (CALI): Calibration enable bit for ADC offset...

  • Page 53: Adc Data Register (Addata/Rb, Addata1H/Rc, Addata1L/Rd)

    6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set. 6.7.3 ADC Sampling Time The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator.

  • Page 54: Programming Process/Considerations

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 3. ADWE bit of the RE register is set to “1.” Wake-up from ADC conversion (where it remains in operation during sleep mode). 4. Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the “DISI”...

  • Page 55: Sample Demo Programs

    In order to obtain accurate values, it is necessary to avoid any data transition on the I/O pins during AD conversion. 6.7.6.2 Sample Demo Programs A. Define a General Register R_0 == 0 PSW == 3 PORT5 == 5 PORT6 == 6 R_E== 0XE B.
  • Page 56 EM78P259N/260N 8-Bit Microprocessor with OTP ROM RETI INITIAL: MOV A,@0B00000001 MOV AISR,A MOV A,@0B00001000 MOV ADCON,A En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others IOW PORT5 MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X” MOV RE,A MOV A, @0BXXXX1XXX ;...

  • Page 57: Infrared Remote Control Application/Pwm Waveform Generation

    6.8 Infrared Remote Control Application/PWM Waveform Generation 6.8.1 Overview This LSI can easily output infrared carrier or PWM standard waveform. As illustrated below, the IR and PWM waveform generation function include an 8-bit down count timer/counter, high time, low time, and IR control register. The IROUT pin waveform is determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high time rate, low time rate control register), IOC81 (TCCC counter), IOCA1 (high time register), and IOC91 (low time register).

  • Page 58: Function Description

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM When an interrupt is generated by the High time down counter underflow (if enabled), the next instruction will be fetched from Address 018 and 01BH (High time and Low time, respectively). 6.8.2 Function Description The following figure shows LGP=0 and HF=1.
  • Page 59 The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low time segments of the pulse. When IRE goes low from high, the output waveform of IROUT will keep transmitting untill high time interrupt occurs. Fcarrier low time width high time width...

  • Page 60: Programming The Related Registers

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM The following figure shows LGP=1 and HF=1. When this bit is set to high level, the high time segment of the pulse is ignored. So, IROUT waveform output is determined by low time width. Fcarrier low time width start...
  • Page 61 EM78P259N/260N 8-Bit Microprocessor with OTP ROM • 55 Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice)

  • Page 62: Timer/Counter

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.9 Timer/Counter 6.9.1 Overview Timer A (TCCA) is an 8-bit clock counter. Timer B (TCCB) is a 16-bit clock counter. Timer C (TCCC) is an 8-bit clock counter that can be extended to 16-bit clock counter with programmable scalers.
  • Page 63 Under TCCBH / MSB Counter (IOC71): TCCBH/MSB (IOC71) is an 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It can be read, written to, and cleared on any reset condition. When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then TCCB is a 16-bit length counter.

  • Page 64: Programming The Related Registers

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.9.3 Programming the Related Registers When defining TCCX, refer to its related registers operation as shown in the tables below. TCCX Related Control Registers: Address Name Bit 7 0x08 IOC80 0x09 IOC90 TCCBHE/0 TCCBEN/0 TCCBTS/0 TCCBTE/0 IR CR 0x0A TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0...

  • Page 65: External Reference Signal

    6.10.1 External Reference Signal The analog signal that is presented at Cin– compares to the signal at Cin+. The digital output (CO) of the comparator is adjusted accordingly by taking the following notes into considerations: ■ The reference signal must be between Vss and Vdd. ■...

  • Page 66: Using A Comparator As An Operation Amplifier

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.10.3 Using a Comparator as an Operation Amplifier The comparator can be used as an operation amplifier if a feedback resistor is externally connected from the input to the output. In this case, the Schmitt trigger can be disabled for power saving purposes, by setting Bit 4, Bit 3<COS1, COS0>...

  • Page 67: Oscillator

    6.11 Oscillator 6.11.1 Oscillator Modes The EM78P259N/260N can be operated in four different oscillator modes, such as High Crystal oscillator mode (HXT), Low Crystal oscillator mode (LXT), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC). You can select one of them by programming the OSC2, OCS1, and OSC0 in the Code Option register.

  • Page 68: Crystal Oscillator/Ceramic Resonators (Crystal)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78P259N/260N can be driven by an external clock signal through the OSCI pin as illustrated below. In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation.

  • Page 69: External Rc Oscillator Mode

    Circuit diagrams for serial and parallel modes Crystal/Resonator: EM78P259N EM78P260N 6.11.3 External RC Oscillator Mode For some applications that do not require precise timing calculation, the RC oscillator (Fig. 6-20 right) could offer you with effective cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by...

  • Page 70: Internal Rc Oscillator Mode

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the way the PCB is layout, have certain effect on the system frequency. The RC Oscillator frequencies: Cext 20 pF...

  • Page 71: Power-On Considerations

    6.12 Power-on Considerations Any microcontroller is not warranted to start operating properly before the power supply stabilizes in its steady state. The EM78P259N/260N POR voltage range is 1.9V ~ 2.1V. Under customer application, when power is switched OFF, Vdd must drop below 1.9V and remains at OFF state for 10μs before power can be switched ON again.

  • Page 72: Residual Voltage Protection

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.12.3 Residual Voltage Protection When the battery is replaced, device power (Vdd) is removed but the residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig. 6-22 and Fig. 6-23 show how to create a protection circuit against residual voltage.

  • Page 73: Code Option

    6.13 Code Option EM78P259N/260N has two Code option words and one Customer ID word that are not part of the normal program memory. Word 0 Bit12 ~ Bit0 6.13.1 Code Option Register (Word 0) Bit 12 Bit 11 Bit 10 Bit 9 –...

  • Page 74: Code Option Register (Word 1)

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 3 (HLP): Bit 2 ~ 0 (PR2 ~ PR0): Protect Bits 6.13.2 Code Option Register (Word 1) Bit 12 Bit 11 Bit 10 RCOUT Bits 12 ~ 11: Bit 10 (RCOUT): Bit 9 (NRHL): The noise rejection function is turned off under the LXT and sleep mode.

  • Page 75: Customer Id Register (Word 2)

    Bit 7 (WDTPS): Bit 6 (CYES): Bits 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits 6.13.3 Customer ID Register (Word 2) Bit 12 Bit 11 Bit 10 Bit 9 Bit 12 ~ 0: Customer’s ID code 6.14 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one...
  • Page 76 EM78P259N/260N 8-Bit Microprocessor with OTP ROM Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation.

  • Page 77: Absolute Maximum Ratings

    Instruction Binary Mnemonic 0 0101 01rr rrrr 05rr INC R 0 0101 10rr rrrr 05rr DJZA R 0 0101 11rr rrrr 05rr DJZ R 0 0110 00rr rrrr 06rr RRCA R 0 0110 01rr rrrr 06rr RRC R 0 0110 10rr rrrr 06rr RLCA R 0 0110 11rr rrrr...

  • Page 78: Dc Electrical Characteristics

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM DC Electrical Characteristics Ta=25 ° C, VDD=5.0V±5%, VSS=0V Symbol Parameter Crystal: VDD to 5V Crystal: VDD to 3V ERC: VDD to 5V Input High Threshold VIHRC Voltage (Schmitt trigger) Input Low Threshold VILRC Voltage (Schmitt trigger) Input Leakage Current for input pins Input High Voltage...
  • Page 79 Symbol Parameter Operating supply current ICC1 at two clocks (VDD to 3V) Operating supply current ICC2 at two clocks (VDD to 3V) Operating supply current ICC3 at two clocks Operating supply current ICC4 at two clocks Note: These parameters are hypothetical, have not been tested and are provided for design reference only. Data in the Minimum, Typical and Maximum (“Min”, Typ”, Max”) columns are based on hypothetical results at 25 °...

  • Page 80: Ad Converter Characteristics

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM 8.1 AD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25 ° C Symbol Parameter AREF Analog reference voltage Analog input voltage Ivdd IAI1 Analog supply current Ivref Ivdd IAI2 Analog supply current IVref OP current Resolution Resolution Linearity error...

  • Page 81: Comparator (Op) Characteristics

    8.2 Comparator (OP) Characteristics Vdd = 5.0V, Vss=0V, Ta=25 ° C Symbol Parameter Slew rate Input offset voltage Input voltage range Output voltage swing Supply current of OP Supply current of Comparator Power-supply Rejection PSRR Ration for OP Operating range Note: These parameters are hypothetical (not tested) and are provided for design reference only.

  • Page 82: Ac Electrical Characteristic

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V AC Electrical Characteristic Ta=25 ° C, VDD=5V±5%, VSS=0V Symbol Parameter Dclk Input CLK duty cycle Instruction cycle time Tins (CLKS="0") Ttcc TCC input period Tdrh Device reset hold time Trst /RESET pulse width...

  • Page 83: Timing Diagrams

    10 Timing Diagrams AC Test Input/Output Waveform VDD-0.5V GND+0.5V AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0". RESET Timing (CLK="0") /RESET TCC Input Timing (CLKS="0") Tins Product Specification (V1.2) 05.18.2007...

  • Page 84: Appendix

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM A Package Type OTP MCU EM78P259NPS/NPJ EM78P259NMS/NMJ EM78P260NPS/NPJ EM78P260NMS/NMJ EM78P260NKMS/NKMJ B Package Information B.1 18-Lead Plastic Dual in line (PDIP) — 300 mil 78 • APPENDIX Package Type Pin Count SSOP θ Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) Package Size 300mil...

  • Page 85: 18-Lead Plastic Small Outline (Sop) - 300 Mil

    B.2 18-Lead Plastic Small Outline (SOP) — 300 mil Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) EM78P259N/260N 8-Bit Microprocessor with OTP ROM Symbal 2.350 0.102 0.230 7.400 10.000 11.350 0.406 θ TITLE: SOP-18L(300MIL) PACKAGE OUTLINE DIMENSION File : SO18...

  • Page 86: 20-Lead Plastic Shrink Small Outline (Ssop) - 209 Mil

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM B.3 20-Lead Plastic Shrink Small Outline (SSOP) — 209 mil 80 • Symbal 0.050 1.620 0.220 0.090 7.400 5.000 6.900 0.650 θ TITLE: SSOP-20L(209MIL) OUTLINE PACKAGE PACKA OUTLINE DIMENSION File : SSOP20 Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) Normal 2.130...

  • Page 87: 20-Lead Plastic Dual-In-Line (Pdip) - 300 Mil

    B.4 20-Lead Plastic Dual-in-line (PDIP) — 300 mil Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) EM78P259N/260N 8-Bit Microprocessor with OTP ROM Symbal Normal 0.381 3.175 3.302 0.203 0.254 25.883 26.060 26.237 6.220 6.438 7.370 7.620 8.510 9.020...

  • Page 88: 20-Lead Plastic Small Outline (Sop) - 300 Mil

    EM78P259N/260N 8-Bit Microprocessor with OTP ROM B.5 20-Lead Plastic Small Outline (SOP) — 300 mil 82 • Symbal 2.350 0.102 0.230 7.400 10.000 12.600 0.630 θ TITLE: SOP-20L(300MIL) PACKAGE OUTLINE DIMENSION File : SO20 Product Specification (V1.2) 05.18.2007 (This specification is subject to change without further notice) Normal 2.650 0.300...

  • Page 89: C Quality Assurance And Reliability

    C Quality Assurance and Reliability Test Category Solder temperature=245±5 ° C, for 5 seconds up to the Solderability stopper using a rosin-type flux Step 1: TCT, 65 ° C (15mins)~150 ° C (15mins), 10 cycles Step 2: Bake at 125 ° C, TD (durance)=24 hrs Step 3: Soak at 30°C/60%，TD (durance)=192 hrs Pre-condition Step 4: IR flow 3 cycles...

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