Kurzweil K2000 Service Manual page 105

SECTION 5
AlJDPWR5.00c 12/22/92
two flip-flops in U49 (A-7) serve to dalay the control signals from U50 to the analog switches
sufficiently to allow for smoother transition from previous value to settling transient to new
value in a more linear fashion and eliminate distortion at low signal levels.
After conversion to sampled analog voltages at Ul5-l and Ul5-7 (D-6 to D-7), the effected audio
signals are filtered by circuitry around U7 (F-6 to G-7). Each filter is two cascaded 3-pole
Butterworth sections identical to the input filter described elsewhere.
After filtering, the audio signals go through voltage-controlled amplifiers at the bottom of
schematic page 4. In order to get the phasing correct with respect to the "dry" signal that
bypasses the Effects Unit, two inverting amplifiers are required in each channel. The first
performs current-to-voltage conversion while the second reinverts the signal's phase and applies
one pole of the high frequency cut to cancel the lower boost pole added at the input mixer. The
high-frequency droop in the AID/A process.
5.1.5.4 EFFECTS LSI CHIP AND DELAY RAM
The Effects LSI chip (USO) is the largest IC on the Audio/Power Board.
mount chip under the RFI shield along with the other digital circuitry.
interface ports.
It is an 84-pin surface-
It has three basic
The MCA (MicroCode Address) and MCD (MicroCode Data) busses form the MicroCode Port which is how
the chip receives instructions for performing any given effects algorithm. Every l25nS a new
microcode address is sent out on the MCA bus and somewhat later the corresponding microcode data
is received from the MCD bus.
The Analog I/O Port consists of the CAC bus and control signals MSREG, LSREG, S&HL, and S&HR.
Sixteen bit values destined for the D/A converter are output 8 bits at a time on the CAC bus and
then latched into Ul7 (E-3) and Ul8 (E-4) under control of MSREG and LSREG. S&HL and S&HR
control the analog routing switches as described earlier.
The Delay RAM port connects directly to 5 DRAM chips for delay line storage. U4l - U45 are each
64K by 4 bit DRAMs and are interconnected to make a 64K word by 20-bit memory. U50 sends out a
l6-bit address multiplexed on 8 address lines (RMA bus) and reads or writes 20-bit data on the
RMD bus. Direct connections for the other DRAM signals (RAS, CAS, and WE) are also provided on
the Delay RAM Port. The DRAMs are always being cycled so their CE pins may be simply grounded.
The sample rate for the effects system is 33.3KS/s (Kilo-Samples per second), which is a sample
period of 30 microseconds. During each sample period it does one AID conversion, two D/A
conversions, and cycles through the algorithm microprogram once. Figure 7 below shows a timing
diagram for one sample period. During the first 3uS the LSI chip closes the input switch (UlO
section A) and samples the input signal. The switch is opened and an additional 3uS elapses
waiting for the Ul2-7 op-amp to settle. The last 24uS is spent outputting l6 trial values and
reading the result from the comparator as described above. Simultaneously the output of the left
channel data is performed for the 3uS while the input is in the sample mode followed by the right
channel for 3uS wile the input op-amp is settling. Then the cycle repeats. The circuit is
always cycling like this even if the Engine Board selects no effects.
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