Advanced Chipset Control - Supermicro X7DWE User Manual

UIO PCI-Exp. x8, Slot1 PCI-X 133 MHz, Slot2 PCI-Exp.
x4, Slot3 PCI-Exp x8, Slot4 PCI-Exp x8, Slot5 PCI-Exp x8,
and Slot6 PCI-Exp x8
Access the submenu for each of the settings above to make changes to the
following:
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for the Bus Master. A high-priority,
high-throughout device may benefi t from a greater clock rate. The options are
Default, 0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix,
Novell and other Operating Systems, please select the option: other. If a drive
fails after the installation of a new software, you might want to change this setting
and try again. A different OS requires a different Bus Master clock rate.
Large Disk Access Mode
This setting determines how large hard drives are to be accessed. The options are
DOS or Other (for Unix, Novelle NetWare and other operating systems).

Advanced Chipset Control

Access the submenu to make changes to the following settings.
Warning
: Take caution when changing the Advanced settings. An Incor-
rect value, a very high DRAM frequency or an incorrect DRAM timing may
cause system to become unstable. When this occurs, reset the setting to
the default setting.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled.
4-11
Chapter 4: BIOS