Pioneer DJM-1000 Service Manual page 150

1
No. Pin Name
A
153 HAS/ACLKX1
145 HCS/AXR0[13]/AXR1[2]
151 HDS1/AXR0[9]/AXR1[6]
150 HDS2/AXR0[10]/AXR1[5]
140 HRDY/ACLKR1
EMIF - COMMON SIGNALS TO ALL TYPES OF MEMORY
57 CE3
61 CE2
B
103 CE1
102 CE0
108 BE1
110 BE0
EMIF - BUS ARBITRATION
137 HOLDA
138 HOLD
136 BUSREQ
EMIF - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
C 78 ECLKIN
77 ECLKOUT
79 ARE/SDCAS/SSADS
75 AOE/SDRAS/SSOE
83 AWE/SDWE/SSWE
56 ARDY
EMIF - ADDRESS
109 EA21
D
101 EA20
100 EA19
95 EA18
99 EA17
92 EA16
94 EA15
90 EA14
91 EA13
93 EA12
86 EA11
76 EA10
E
74 EA9
71 EA8
70 EA7
69 EA6
68 EA5
64 EA4
63 EA3
62 EA2
F
150
1
2
I/O
I Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z).
Host chip select (I) [default] or McASP0 TX/RX pin 13 (I/O/Z) or McASP1 TX/RX pin 2 (I/O/Z).
I
Host data strobe 1 (I) [default] or McASP0 TX/RX pin 9 (I/O/Z) or McASP1 TX/RX pin 6 (I/O/Z).
I
Host data strobe 2 (I) [default] or McASP0 TX/RX pin 10 (I/O/Z) or McASP1 TX/RX pin 5 (I/O/Z).
I
O/Z Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
O/Z Memory space enables
O/Z
• Enabled by bits 28 through 31 of the word address
• Only one asserted during any external data access
O/Z
O/Z
O/Z Byte-enable control
• Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory
O/Z
• Can be directly connected to SDRAM read and write mask signal (SDQM)
O/Z Hold-request-acknowledge to the host
I Hold request from the host
O/Z Bus request output
I External EMIF input clock source
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]).
EKSRC = 0 - ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default).
O/Z EKSRC = 1 - ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN)
EKEN = 0 - ECLKOUT held low
EKEN = 1 - ECLKOUT enabled to clock (default)
O/Z Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe
O/Z Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
O/Z Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
I Asynchronous memory ready input
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
External address ( word, half-word, and byte address) The EMIF adjusts the address based on
memory width:
O/Z
Width Pins
O/Z
32 21:2
O/Z
16 21:2
O/Z
8 21:2
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
DJM-1000
2
3
Pin Function
Address
21 through 2
20 through 1
19 through 0
3
4
4