LG GCC-4242N Service Manual page 37

FUNCTIONAL BLOCK DIAGRAM
CLK
ADD
LCKE
LRAS
CLK CKE
•Pin Function Description
Pin Name
CLK System Clock
CS Chip Select
CKE Clock Enable
A0~A10/AP Address
BA Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ0~15 Data Input/Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide inproved noise
N.C/RFU No Connection/
Reserved for Future Use
Bank Select
LCBR LWE LCAS
Timing Register
CS RAS CAS
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK, CKE
and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge fof the CLK with CAS low.
Enables column access.
Enable write operation and row precharge.
Latches data in starting from CAS, WE active.
Make data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
immunity.
This pin is recommended to be left No Connection on the device.
Data Input Register
512 x 16
512 x 16
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
WE L(U)DQM
LWE
LDQM
DQi
LDQM
39