LG GCC-4242N Service Manual page 36

IC601 (M12L16161A) : SDRAM
Overview
The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2x 524,288
words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle
control with the use of system clock I/O transactions are possible on every clock cycle. Range for operating
frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
• PIN CONFIGURATION (TOP VIEW)
38
V
1
DD
DQ0
2
DQ1
3
V
4
SSQ
DQ2
5
DQ3
6
V
7
DDQ
DQ4
8
DQ5
9
V 10
SSQ
DQ6 11
DQ7
12
V 13
DDQ
LDQM 14
WE
15
CAS
16
RAS
17
CS 18
BA 19
A10/AP
20
A0
21
A1 22
A2
23
A3 24
V 25
DD
V
50
SS
49
DQ15
48 DQ14
V
47
SSQ
46
DQ13
45
DQ12
V
44
DDQ
DQ11
43
DQ10
42
V
41
SSQ
DQ9
40
DQ8
39
V
38
DDQ
N.C/RFU
37
UDQM
36
CLK
35
CKE
34
N.C
33
A9
32
A8
31
A7
30
50PIN TSOP(II)
A6
29
(400mil x 825mil)
A5
28
(0.8 mm PIN PITCH
A4
27
V
26
SS