Sony CDP-XA50ES Service Manual page 35

Pin No. Pin Name I / O
44 WDCK O
45 LRCK O
46 DATA O
47 BCLK O
48 64 DATA O
49 64 BCLK O
50 64 LRCK O
51 GTOP O
52 XUGF O
53 XPLCK O
54 GFS O
55 RFCK O
56 C2PO O
57 XRAOF O
58 MNT3 O
59 MNT2 O
60 MNT1 O
61 MNT0 O
62 XTAI I
63 XTAO O
64 XTSL I
65 DVSS —
66 FSTI I
67 FSTO O
68 C4M O
69 C16M O
70 MD2 I
71 DOUT O
72 EMPH O
73 WFCK O
74 SCOR O
Word clock signal (88.2 kHz) output terminal
L/R sampling clock signal (44.1 kHz) output to the CXD8679Q (IC601)
DA16 output when PSSL="H", 48-bit slot serial data output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA15 output when PSSL="H", 48-bit slot bit clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA14 output when PSSL="H", 64-bit slot serial data output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA13 output when PSSL="H", 64-bit slot bit clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA12 output when PSSL="H", 64-bit slot L/R sampling clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA11 output when PSSL="H", GTOP signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA10 output when PSSL="H", XUGF signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA09 output when PSSL="H", XPLCK signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA08 output when PSSL="H", GFS (guard frame sync) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA07 output when PSSL="H", RFCK (read frame clock) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA06 output when PSSL="H", C2PO signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA05 output when PSSL="H", XRAOF (RAM over flow) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA04 output when PSSL="H", MNT3 (monitor 3) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA03 output when PSSL="H", MNT2 (monitor 2) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA02 output when PSSL="H", MNT1 (monitor 1) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA01 output when PSSL="H", MNT0 (monitor 0) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
System clock input terminal (16 MHz)
System clock output terminal (16 MHz)
System clock selection input terminal (fixed at "L")
Ground terminal (digital system)
2/3 divider input terminal of pins ^™ (XATI) and ^£ (XTAO)
2/3 divider output terminal of pins ^™ (XATI) and ^£ (XTAO)
4.2336 MHz clock signal output terminal Not used (open)
16.9344 MHz clock signal output terminal Not used (open)
Digital out on/off control signal input from the system controller (IC201)
Digital signal (for coaxial out and optical out) output terminal
Emphasis control signal output terminal
Write frame clock signal output terminal
Sub-code sync (S0+S1) detection signal output to the system controller (IC201)
– 55 –
Function
Not used (open)
Serial data output to the CXD8679Q (IC601)
Bit clock signal (2.8224 MHz) output to the CXD8679Q (IC601)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)