LG GCC-4520B Service Manual page 44

171 HRST#
147, 149, 151,
HD15~HD0
153, 156, 159,
161, 166, 167,
164, 160, 158,
155, 152, 150,
148
146 DMARQ
145 DIOW#
144 DIOR#
143 IORDY
141 DMACK#
140 INTRQ
138 IOCS16#
Host reset input. The active-low input is referred to as hardware
3.3V LVTTL Input,
reset and is used to reset this chip.
SMT,75K pull-up
Host Data bus. This is the 8-bit or 16-bit bi-directioinal data bus to
3.3V LVTTL I/O
the host. The lower 8 bits, HD0~HD7, are used for 8-bit data
Slew rate, SMT,
transfers. Normally, data transfers are 16-bit wide.
2mA, 4mA, 6mA,
8mA, 10mA PDR,
Note : All pins except HD7 (no any pull) may be selectively pull-up
40K PPU,
40K PPD
Default : 6mA, pull-up.
DMA request. This signal is used for DMA data transfers between
3.3V LVTTL I/O,
host and device and it shall be asserted by the MT1618 when it is
Slew rate,
ready to transfer data to or from the host. The direction of data
10mA driving
transfer is controlled by DIOR# and DIOW#.
Device I/O write. Stop ultra DMA burst.
3.3V LVTTL Input,
For Device I/O Write, this signal is the strobe signal asserted by
SMT,
the host to write device register or the data port.
40K pull-up
For Stop, Ultra DMA, this signal shall be negated by the host
before data is transferred in an Ultra DMA burst and is asserted
by host during an Ultra DMA burst to signal the termination of
Ultra DMA burst.
Device I/O read. Ultra DMA ready. Ultra DMA data strobe.
3.3V LVTTL Input,
SMT,
For Device I/O Read, this signal is the strobe signal asserted by
40K pull-up
the host to read device registers or the data port.
For Ultra DMA Ready, this is asserted by the host to indicate to
the device that the host is ready to receive Ultra DMA data in
burst to the host.
For Ultra DMA data strobe, this signal is the data out strobe signal
from the host for an Ultra DMA data out burst.
I/O Channel Ready. Ultra DMA ready. Ultra DMA data strobe.
3.3V LVTTL I/O,
Slew rate,
For I/O channel Ready, this signal is negated to extend the host
10mA driving
transfer cycle of any register read or write when the device is not
able to complete the transfer.
For Ultra DMA Ready, this is asserted by the device to indicate to
the host that the device is ready to receive Ultra DMA data out
burst from the host.
For Ultra DMA data strobe, this is the data in strobe signal from
device for Ultra DMA data in burst to the host.
DMA Acknowledge. This signal shall be used by the host in
3.3V LVTTL Input,
response to DMARQ to acknowledge that it is ready for DMA
SMT,
transfers.
40K pull-up
Device Interrupt. This signal is used to interrrupt the host system.
3.3V LVTTL I/O,
INTRQ is driven only when this chip is addressed. When not
Slew rate,
driven, INTRQ is in a high impedance state.
10mA driving, SMT
Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16#
3.3V LVTTL output,
indicates to the host system that the 16-bit data port has been
Slew rate,
addressed and that the device is prepared to send or receive a
10mA driving,
16-bit data word.
(open-drain)
or pull-down with 40K resistant.
47