Sony DVP-CX985V Service Manual page 106

DVP-CX985V
Pin No. Pin Name
134 to141 D0 to D7
142 VDD3.3V
143, 144 PWM0, PWM1
145 VSS
146 PWM2
147 DFCT
148 MIRR
149 VDD1.8V
150 CLKIN
151 VSS
152 TZC
153 GIO0/INT2
154 GIO1/INT3
155 GIO2/INT4
156 GIO3/INT5
157 GIO4/PGREF
158 GIO5/PGIN
159 GIO6/SDI
160 VDD3.3V
161 GIO7/SDO
162 GIO8/SCK
163 GIO9/FGREF
164 GIO10/FGIN
165 GIO11/TMC2
166 GIO12
167 GIO13
168 VSS
169 DATA/EMU1
170 BCLK/EMU1
171 TRST
172 TMS
173 TDI
174 TCK
175 LRCK/TDO
176 VDD1.8V
106
I/O
I/O Two-way data bus terminal
—
Power supply terminal (+3.3V) (for digital system)
O
Sled motor drive signal output terminal
—
Ground terminal (for digital system)
O PWM signal output terminal
I
Defect signal input from the RF amplifier
I
Mirror signal input from the RF amplifier
—
Power supply terminal (+1.8V) (for digital system)
I Clock signal input from the clock generator
—
Ground terminal (for digital system)
I
Tracking zero crossing signal input from the RF amplifier
I
Limit in detect switch input terminal
O Spindle motor drive control signal output terminal
O
Thermal shut down signal output to the motor/coil driver
I/O
Not used
I/O
Not used
I Signal detection signal input from the RF amplifier
I
Serial data input from the RF amplifier
—
Power supply terminal (+3.3V) (for digital system)
O
Serial data output to the RF amplifier
O Serial clock signal output to the RF amplifier
I/O
Not used
I/O
Not used
O
Interruption control signal output to the RF amplifier
I/O Not used
O
Serial data enable signal output to the RF amplifier
—
Ground terminal (for digital system)
O
Serial data output to the AV decoder
O Bit clock signal output to the AV decoder
I
Reset signal input from the interface controller
I
Mode selection signal input terminal
I
Serial data input from the mechanism controller
I Clock signal input terminal
O
L/R sampling clock signal output to the AV decoder and serial data output to the DSD decoder
—
Power supply terminal (+1.8V) (for digital system)
Description