Sharp ER-A440 Service Manual page 16

Pin SIGNAL
SYMBOL
No. NAME
33 KR7 KR7
34 AVRF GND
35 AVDD VDD
36 /RESET /RES0
37 XT2
38 XT1
39 IC GND
40 X2
41 X1
42 VSS1 GND
43 LDRQ LDRQ
44 ERC ERC
45 SHEN /SHEN
46 /RES1 /RESETS
47 ST6 ST6
48 ST7 ST7
49 ST8 ST8
50 ST9 NU
51 /POFF /POFF
52 BUZ BUZ
53 T0 G1
54 T1 G2
55 T2 G3
56 T3 G4
57 T4 G5
58 T5 G6
59 T6 G7
60 T7 G8
61 T8 G9
62 T9 G10
63 T10 NU
64 ID NU
3. Clock generator
1) CPU (HD64151010FX)
XTAL
CPU
(HD64151010FX)
EXTAL
Basic clock is supplied from a 14.7456MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
IN/
FUNCTION
OUT
IN KEY RETURN 7
IN
32. 768 KHz
4. 19 M Hz
IN LORD REQUEST
IN EVENT READ CANCEL
OUT SHIFT ENABLE
OUT SYSTEM TO RESET
OUT KEY STROBE 6
OUT KEY STROBE 7
OUT KEY STROBE 8
OUT KEY STROBE 9
IN POWER OFF
OUT BUZZER
OUT DISPLAY DIGIT 1
OUT DISPLAY DIGIT 2
OUT DISPLAY DIGIT 3
OUT DISPLAY DIGIT 4
OUT DISPLAY DIGIT 5
OUT DISPLAY DIGIT 6
OUT DISPLAY DIGIT 7
OUT DISPLAY DIGIT 8
OUT DISPLAY DIGIT 9
OUT DISPLAY DIGIT 10
OUT DISPLAY DIGIT 11
OUT DISPLAY SEGMENT
X1
99
14.7456MHz
98
101
PHAI
Fig. 3-1
2) CKDC8 oscillation circuit
CKDC 8
XT2
XT1
HD404728A91FS
Two oscillators are connected to the CKDC8.
The main clock X3 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
MPCA7
C208
1µ 50V
13 54 48
POFF
89
1
IRQ0
RESET (FROM CKDC 8)
CPU
72
STOP (TO CKDC 8)
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
4 – 9
40
X2
41
X1
R164
330K
37
X2
32.768KHz
38
C106
18P
Fig. 3-2
+24V
1SS133
R12
R11
8.2KG
2.7K
R10
R13 56K
15KG
8
3 B
+
+ 1
2
-
IC3A
4
R14 KIA393F
ZD2
9.1KG
MTZ5.1A
Fig. 4-1
X3
4.19MHz
1
2
3
C105
33P
+5V
D7
R9
2.7K
/POFF
C3
1000P