MSI NF750-G55 seres User Manual page 45

▶ tRP
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s
adjustable. Ths settng controls the number of cycles for Row Address Strobe (RAS)
to be allowed to precharge. If nsufficent tme s allowed for the RAS to accumulate
ts charge before DRAM refresh may be ncomplete and DRAM may fal to retan
data. Ths tem apples only when synchronous DRAM s nstalled n the system.
▶ tRAS
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s
adjustable. Ths settng determnes the tme RAS takes to read from and wrte to a
memory cell.
▶ tRTP
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s
adjustable. Ths settng controls the tme nterval between a read and a precharge
command.
▶ tRC
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s
adjustable. The row cycle tme determnes the mnmum number of clock cycles a
memory row takes to complete a full cycle, from row actvaton up to the prechargng
of the actve row.
▶ tWR
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s
adjustable. It specfies the amount of delay (n clock cycles) that must elapse after
the completon of a vald wrte operaton, before an actve bank can be precharged.
Ths delay s requred to guarantee that data n the wrte buffers can be wrtten to the
memory cells before precharge occurs.
▶ tRRD
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s
adjustable. Specfies the actve-to-actve delay of dfferent banks.
▶ tWTR
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjustable.
Ths tem controls the Wrte Data In to Read Command Delay memory tmng. Ths
consttutes the mnmum number of clock cycles that must occur between the last
vald wrte operaton and the next read command to the same nternal bank of the
DDR devce.
▶ tRFC0~3
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], these fields are
adjustable. These settngs determne the tme RFC take to read from and wrte to
memory cells.
▶ 1T/2T Memory Tmng
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjustable.
Ths field controls the SDRAM command rate. Selectng [1T] makes SDRAM sgnal
controller to run at 1T (T=clock cycles) rate. Selectng [2T] makes SDRAM sgnal
controller run at 2T rate.
▶ DCT Unganged Mode
Ths feature s used to Integrate two 64-bt DCTs nto a 128-bt nterface.
Englsh
En-35