Fpga Signal Timing - Fujitsu MB86R11 Hardware Manual

MB86R11 Evaluation Board
MB86R11EVB Hardware Manual
5.2.6.

FPGA signal timing

FPGA signal timing is shown as follows.
MEM_CLK
MEM_XCS[1]
MEM_XRD
MEM_XWRx
MEM_EA[11:0]
MEM_ED[ 3 1:0]
MEMCS register min setting
RACC : 1 (2cycle)
RADC : 0 (0cycle)
RIDLC : 0(1cycle)
WACC : 2(3cycle)
WADC : 0(1cycle)
WWEC : 0(1cycle)
WIDLC : 0(1cycle)
Remarks
The frequency of MEM_CLK is 100MHz less.
The half word and word can be access.
FPGA is the connection of MEM_EA[11:1]. MEM_EA[26:12] is not decode.
The register of 00-08h address can be read any time.
The judgment of the 16bit/32bit connection of the Ex-bus width uses MPXMODE[2].
RIDLC
0XX
Read
Data
Read
Figure 5-1 Access timing
72
WIDLC
0XX
Write Data
Write
9. Allocation of peripheral resource
and I2C port