Chipset; Overview; Amd I/O Bridges; Hypertransport 3 (Ht3) - Dell PowerEdge R515 Technical Manual

Dell

7 Chipset

7.1 Overview

The PowerEdge R515 planar uses a dual IOB configuration using the AMD SR5670 chipset with IO bridges and
the SP5100 Southbridge. The SR5670 is designed to support the AMD C32 processor family, HyperTransport-3
Interface (@ 2.6GHz), DDR3 memory technology, and PCI Express Generation 2. The chipset consists of the
SR5670 and the SP5100.

7.2 AMD I/O Bridges

The PowerEdge R515 I/O board uses the AMD SR5670 I/O Bridges (IOB) to provide links between the C32
processor(s) and I/O components. The main components of the I/O controllers are configured to use two x16
HyperTransport 3 links (to both processors), up to 42 lanes of PCI Express Gen 2, an x4 PCIe Gen 1
Southbridge Interface (SB Link) and an integrated IOAPIC.

7.3 HyperTransport 3 (HT3)

The HyperTransport 3 (HT3) consists of serial point-to-point interconnects for the processors and the I/O
bridges. The PowerEdge R515 has a total of four HT3 links per processor which allows interconnecting each
processor with each other and an option for I/O Bridge. Each I/O Bridge has a single x16 HT3 link. A full link
consists of 16 lanes (full-width) in each direction with a link speed of 6.4 GT/s. The HT3 clocking for
processor HT3 and IOB HT3 are 3.2 GHz and 2.6 GHz, respectively. Therefore, the IOB HT3 link is capable of
5.2 GT/s. For routing, the HT3 links are grouped by x8 Command Address (CAD), x1 Control (CTL), and x1
Clock (CLK) for each RX and TX directions.

7.4 Southbridge Link Interface

The Southbridge (SB) link connects the SR5670 IOB with the AMD Southbridge SP5100. The SB Link (A-Link
Express) is equivalent to an x4 PCIe Gen 1 link with a transfer rate of 1 GB/s in each direction.

7.5 AMD SP5100 Southbridge (SP5100)

SP5100 is a highly integrated Southbridge controller, supporting the following functions:

PCI bus 32-bit interface Rev 2.3 running at 33 MT/s
o Serial ATA (SATA) ports with transfer rates up to 300 MB/s (R515 supports one SATA port for
optical devices)
o Five OHC (full-speed 1.1) and two EHCI (high-speed 2.0) USB host controllers, with up to 12
USB general purpose ports and 2 USB embedded ports (R515 uses 6 ports for internal and
external use from the general purpose ports)

Power management interface (ACPI 3.0b compliant)

Integrated Micro Controller (IMC) and thermal management
Note: The iDRAC interfaces the Hardware Thermal Control (HTC), not the SP5100.

I/O interrupt controller

SMBus 2.0 controller

Low Pin Count (LPC) interface to Super I/O, Trusted Platform Module (TPM), and SPI-VU

Serial Peripheral Interface (SPI) support for up to two devices

4 MB BIOS flash connected to the SP5100 using SPI interface
PowerEdge R515 Technical Guide
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