5.7 Voltage Regulator Adjustments
JP1, a 10–pin header on the Voltage Regulator board, sets the time between program fail-
ure and carrier turnoff. Pins 1 and 2 are the two pins closest to the edge of the board. The
times are approximate. Sections 2.11, 2.12, and 4.8 contain further information.
1. Short pins 1 and 2 for a 30–second delay.
2. Short pins 3 and 4 for a 2–minute delay.
3. Short pins 5 and 6 for a 4–minute delay.
4. Short pins 7 and 8 for an 8–minute delay.
You may select other times by changing the value of R21. The time is proportional to the re-
sistance.
5.8 Bias Set (RF Power Amplifier)
The Bias Set trim pot is located inside the PA module on the input circuit board. Set the trim
pot to its midpoint for near-optimum bias.
5-6
FM30/FM150/FM300 User's Manual