Pbsram (Pipelined Burst Sram); Dimm; Pc-1600 Or Pc-2100 Or Pc-2700 Ddr Dram; Pci (Peripheral Component Interface) Bus - AOpen AX4LR Manual

A X 4 L R / A X 4 L R
A X 4 L R / A X 4 L R
P B S R A M ( P i p e l i n e
P B S R A M ( P i p e l i n e
For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address
decoding time and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is 3-1-1-1,
total 6 clocks, which is faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and
Socket 370 CPU do not need PBSRAM.
P P C C - - 1 1 0 0 0 0 D D I I M M M M
SDRAM DIMM that supports 100MHz CPU
P P C C - - 1 1 3 3 3 3 D D I I M M M M
SDRAM DIMM that supports 133MHz CPU
P C - 1 6 0 0 o r P C - 2 1 0
P C - 1 6 0 0 o r P C - 2 1 0
Based on FSB frequency, the DDR DRAM has 200MHz, 266MHz and 333 MHz three types of working frequency. Because of DDR
DRAM data bus is 64-bit, it provides data transfer bandwidth up to 200x64/8=1600MB/s, and 266x64/8=2100MB/s, and
333x64/8=2700MB/s. Hence, the PC-1600 DDR DRAM is working with 100MHz, PC-2100 DDR DRAM is working with 133MHz and
PC-2700 DDR DRAM is working with 166MHz FSB frequency.
P C I ( P e r i p h e r a l C o
P C I ( P e r i p h e r a l C o
Bus for the internal connection of peripheral devices, high-speed data channel between the computer and expansion card.
- N
- N
d B u r s t S R A M )
d B u r s t S R A M )
FSB bus clock.
FSB bus clock.
0 o r P C - 2 7 0 0 D D R
0 o r P C - 2 7 0 0 D D R
m p o n e n t I n t e r f a c e
m p o n e n t I n t e r f a c e
D R A M
D R A M
) B u s
) B u s
100
O n l i n e M a n u a l
O n l i n e M a n u a l