Advanced Chipset Features - Abit KN8-SLI User Manual

BIOS Setup

3-4. Advanced Chipset Features

Phoenix – Award WorkstationBIOS CMOS Setup Utility
HT Frequency
► DRAM Configuration
SSE/SSE2 Instructions
System BIOS Cachable
↑↓:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
HT Frequency:
This item selects the LDT Bus Frequency.
# DRAM Configuration:
Click <Enter> key to enter its submenu:
Phoenix – Award WorkstationBIOS CMOS Setup Utility
DRAM Timing Selectable
X - DRAM Clock
X - CAS latency Time
X - Row Cycle Time
X - Row Refresh Cycle Time
X - Min RAS# Active time
X - RAS# to CAS# delay
X - RAS# Precharge Time
X - RAS# to RAS# delay
X - Write Recovery Time
X - Write to Read Delay
X - Read to Write Delay
X - DRAM Command rate
X - Read Preamble value
X - Max. Async Latency value
X - Bank Interleaving
X - Burst Length
X - DRAM Drive Strength
X - Force 64-bit mode always
X - R/W Queue Bypass Counter.
X - Bypass Max
X - Idle Cycle Limit(ILD-Lmt)
X - Dynamic Idle Cycle Count.
MTRR mapping mode
32 bit Dram Memory Hole
↑↓:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
Advanced Chipset Features
AUTO
Press Enter
Enable
Disable
F6: Fail-Safe Defaults
DRAM Configuration
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Auto
Enabled
4 beats
Drive
Disabled
8
4
16 Cycles
Enabled
Continuous
Auto
F6: Fail-Safe Defaults
Item Help
F7: Optimized Defaults
Item Help
F7: Optimized Defaults
User's Manual
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