Data Error Token; Clearing Status Bits; Card Registers; Spi Bus Timing Diagrams - SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Product Manual

SPI Protocol Definition
Note that this format is used only for Multiple Block Write. In case of Multiple Block Read the stop transmission is
done using STOP_TRAN Command (CMD12).

5.2.5. Data Error Token

If a read operation fails and the card cannot provide the required data it will send a data error token, instead. This
token is one byte long and has the format shown in Figure 5-10.
The four least significant bits (LSB) are the same error bits as in response format R2.

5.2.6. Clearing Status Bits

As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different formats:
response R1, response R2 and data error token (the same bits may exist in multiple response types—e.g., Card ECC
failed). As in the SD mode, error bits are cleared when read by the host, regardless of the response format.

5.3. Card Registers

In SPI Mode, only the OCR, CSD and CID registers are accessible. Their format is identical to their format in the
SD Card mode. However, a few fields are irrelevant in SPI mode.

5.4. SPI Bus Timing Diagrams

All timing diagrams use the schematics and abbreviations listed in Table 5-5.
5-16
1 1 1 1 1 1 0 1
7
0 0 0
Figure 5-10. Data Error Token
SanDisk Secure Digital (SD) Card Product Manual, Rev. 1.9 © 2003 SANDISK CORPORATION
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