Memory Latency - HP Itanium RX7620-16 Manual

Within the cell, CPU-to-CC peak bandwidth is 12.8 GB/s, a greater than 50% improvement over
previous-generation systems.
The minimum supported cell configuration is two active processors and 2 GB of memory per cell
board. The maximum configuration includes eight active processors and 64 GB memory per cell
board in the Integrity rx7620-16 Server; the Integrity rx8620-32 Server supports a maximum of 16
active processors and 64 GB memory per cell board. Memory DIMM modules are sold in sets of four
(quads), with available DIMM sizes of 512 MB, 1 GB, 2 GB, and 4 GB. Memory quads of different
sizes can be mixed within a chassis and within a cell. However, for optimum memory interleaving
and performance, it is recommended that one memory size be selected, distributed evenly across
available cells, and loaded in increments of eight DIMMs (two quads).
Within a cell, the CC-to-memory peak bandwidth is 16 GB/s, a 4X improvement compared to earlier
releases. Memory is accessed directly through the CC, so all memory slots are accessed regardless of
the number of processors loaded on the cell.

Memory latency

There are two types of memory latency within the HP Integrity rx7620-16 Server:
• Memory latency within the cell refers to the case where an application either runs on a partition that
consists of a single cell or uses cell local memory.
• Memory latency between cells refers to the case where the partition consists of two cells and cell
interleaved memory is used. In this case, 50% of the addresses are to memory on the same cell as
the requesting processor, and the other 50% of the addresses are to memory on the other cell.
The HP Integrity rx7620-16 Server average memory latency depends on the number of processors in
the partition. Assuming that memory accesses are equally distributed across all cell boards and
memory controllers within the partition, the average idle memory latency (load-to-use) is as shown
here:
Number of processors per partition
4 processors (one cell)
8 processors (two cells)
There are two types of memory latency within the HP Integrity rx8620-32 Server:
• Memory latency within the cell refers to the case where an application either runs on a partition that
consists of a single cell or uses cell local memory.
• Memory latency between cells refers to the case where the partition consists of two or more cells
and cell interleaved memory is used. For example, for an Integrity rx8620-32 Server with four cells
in the partition, 25% of the addresses are to memory on the same cell as the requesting processor,
and the other 75% of the addresses are to memory on the other three cells.
The HP Integrity rx8620-32 Server's average memory latency depends on the number of CPUs in the
partition. Assuming that memory accesses are equally distributed across all cell boards and memory
controllers within the partition, the average idle memory latency (load-to-use) is as shown here:
Number of processors per partition
4 processors (one cell)
8 processors (two cells)
12 processors (three cells)
16 processors (four cells)
Average memory latency
~241 ns
~292 ns
Average memory latency
~241 ns
~324 ns
~352 ns
~366 ns
14