Chipset Menu; Southbridge Configuration - Biostar A960G Manual

A960G+ / A960GL+ BIOS Manual

5 Chipset Menu

This submenu allows you to configure the specific features of the chipset installed on
your system. This chipset manage bus speeds and access to system memory
resources, such as DRAM. It also coordinates communications with the PCI bus.
Main Advanced
Advanced Chipset Settings
> SouthBridge Configuration
> Northbridge Configuration
> OnBoard Peripherals Configuration
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.

SouthBridge Configuration

SouthBridge Chipset Configuration
SB CIMx Version :
> SB Azalia Audio Configuration
> EC Configuration
OHCI HC(Bus 0 Dev 18 Fn 0)
OHCI HC(Bus 0 Dev 18 Fn 1)
EHCI HC(Bus 0 Dev 18 Fn 2)
OHCI HC(Bus 0 Dev 19 Fn 0)
OHCI HC(Bus 0 Dev 19 Fn 1)
EHCI HC(Bus 0 Dev 19 Fn 2)
OHCI HC(Bus 0 Dev 20 Fn 5)
OnChip SATA Channel
OnChip SATA Type
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
BIOS SETUP UTILITY
PCIPnP Boot Chipset
BIOS SETUP UTILITY
Chipset
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Native IDE]
19
Performance Exit
Options for SB
Select Screen
Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
Exit
ESC
Options for SB HD
Azalia
Select Screen
Select Item
Go to Sub Screen
Enter
F1 General Help
Save and Exit
F10
ESC Exit