TYAN S1854 Trinity 400 User Manual page 47

Setting Option
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
SDRAM Cycle Length
DRAM Clock
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
CPU IOQ Size
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP Driving Control
AGP Driving Value
AGP-4x Mode
OnChip USB
USB Keyboard Support
Auto Detect DIMM/PC2 CLK
CPU Clock/Spread Spectrum
BIOS Def ault Setup Def ault
SDRAM 10ns SDRAM 10ns
SDRAM 10ns SDRAM 10ns
SDRAM 10ns SDRAM 10ns
3 3
Host CLK 33M Host CLK-33M
Disabled Disabled
Enabled Enabled
Disabled Enabled
1 Level 1 Level
Disabled Enabled
Disabled Enabled
64M 64M
Manual Manual
EC EC
Disabled Disabled
Enabled Enabled
Disabled Disabled
Enabled Disabled
Default Default