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PDSBA-Q+/PDSBA+/PDSBA/PDSBE User's Manual
CPU Front Side Bus Speed
JFSB1 and JFSB2 allow you to set the
Front Side Bus Frequency. See the table
on the right for pin definitions. (Default
is Auto.)
PCI/PCI-E Slots to SMB Speeds
2
Jumpers JI
C1/JI
nect PCI/PCI-Exp. slots to the System
Management Bus
open to disable the connection. See the
table on the right for jumper settings.
JPWAKE
KB/MS
4-PinPWR
Processor
A
USB3/4/5/6
USB1/2
LAN
Clock
Slot7
PCI-E x1
LAN
Slot6
PCI-E x16
CTRL
Slot5
PCI-E x4
JI
2
C1
JI
C2
2
Slot4
PCI-33MHz
HDA
Slot3
PCI-33MHz
CD1
Slot2
PCI-33MHz
COM2
J12
Slot1
PCI-33MHz
2
C2 allow you to con-
.
The default setting is
Intel
North Bridge
J B T 1
F W H
B
Intel
South Bridge
I - S A T A 1
I - S A T A 0
J44
Buzzer
USB9/10
USB7/8
I T E
IDE#1
WOL
2-20
CPU FSB Jumper Settings
Jumper Settings
JFSB2
1-2
2-3
Open
2-3
SMBus to PCI-X/PCI-Exp Slots
Jumper Settings
Jumper Setting
Closed
Open
Battery
J P 3
J W D
JLED
I - S A T A 5
I - S A T A 4
J45
LE1
RAIDLED
JL1
IDE#2
JFSB1
Frequency
1-2
*Auto
2-3
266MHz
2-3
200MHz
Open
133MHz
Definition
Enabled
Disabled (*Default)
A. FSB CPU Speeds
B. PCI slots to SMB
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