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EN 46
7.
Q549.2E LA
TS in from
channel decoder
TS out/in for
PCMCIA
DV-ITU-656
CVBS, Y/C,
RGB
Low-IF
SSIF, LR
Dual SPDIF
2
I
S
Dual HDMI
7.5.1
Video Subsystem
Refer to
Figure 7-8
for the main video interfaces for the
PNX8543 and the video signal flow between blocks and
memory.
2009-May-08
Circuit Descriptions
PNX8543x
MPEG
SYSTEM
CI/CA
PROCESSOR
DV INPUT
VIDEO
3D COMB
DECODER
DIGITAL IF
MPEG/H.264
VIDEO
DECODER
AUDIO DEMOD
AND DECODE
AUDIO IN
HDMI
RECEIVER
SYSTEM
300 MHz
CONTROLLER
MIPS32 4KEc
(8051)
CPU
2
I
C
GPIO
IR
ADC
x
2
2
Figure 7-7 PNX8543 functional diagram
MEMORY
CONTROLLER
PRIMARY
VIDEO
OUTPUT
AV-PIP
SUB-PICTURE
SECONDARY
VIDEO
OUTPUT
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DSP
300 MHz
AV-DSP
DRAWING
ENGINE
DMA BLOCK
2
SPI
UART
I
C
GPIO Flash
x
1
0
LVDS for
flat panel display
LVDS
(single or dual
channel)
VIDEO
analog CVBS
ENCODER
AUDIO DACS
analog audio
2
I
S
AUDIO OUT
SPDIF
USB 2.0 CA
PCI 2.2
18440_202_090226.eps
090226
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