Epson DFX-8000 Service Manual page 80

2.3.1 Interface Circuit
i
Figure 2-15 shows a block diagram of the interface circuit.
This section describes the data flow when data is input or output via each interface.
Parallel interface
When the E05A38NA gate array latches the data from the host computer (upon receiving the STRB
signal), it automatically outputs the BUSY signal. The CPU reads the software BUSY status by reading
an MMIO port, and stores the data in the input buffer. After the CPU checks the data, it causes the
Serial interface
The receive data RXD (RECEIVE DATA) from the host computer and the bit 7 data from the 8-bit
parallel interface (when optional serial interface #8 143 is used) are multiplexed using the internal
logic of the E05A16GA gate array, and is output to the CPU asynchronous serial communication
interface (ASCI).
The data is transferred from the CPU to the input buffer.
The transmit data TXD (TRANSMIT DATA) is output directly from the ASCI in the CPU.
In the case of the DC l/DC3 protocol, the DC3 code is output when the buffer becomes
DC 1 code is output when the buffer is ready for more data.)
The REV signal (same as DTR: DATA TERMINAL READY) is output on the same line as the parallel
interface BUSY signal, and performs DTR control. Therefore, the parallel and serial interfaces cannot
be used at the same time.
Printing is started when the CR code is input or the buffer becomes full. The data in the input buffer
is expanded into the line edit buffer, and the image data referenced by each parameter of the line
edit buffer is expanded into the image buffer (by accessing the CG). The expanded image data is
transferred to the E05A38NA gate array in units of 8 bits, and becomes the print data.
- CN 2
1
1
1
PARALLEL l/F
1
1
1
1
1
E05A16GA
I
1
1
1
- - - - -
1
1
J
Figure 2-15. Interface Circuit
2-23
CPU
DATA BUS
ADO-7
T
1
, REV
SERIAL l/F
Block Diagram
full. (The
RAM AR
INPUT
LINE
IMAGE
PROM