Nintendo DMG-01 - Game Boy Console Manual page 51

TM
Game Boy CPU Manual
29. FF26 (NR 52)
Name
Contents - Sound on/off (R/W)
30. FF30 - FF3F (Wave Pattern RAM)
Name
Contents - Waveform storage for arbitrary sound data
31. FF40 (LCDC)
Name
Contents - LCD Control (R/W)
Bit 7 - LCD Control Operation *
by DP
- NR 52 (Value at reset: $F1-GB, $F0-SGB)
Bit 7 - All sound on/off
0: stop all sound circuits
1: operate all sound circuits
Bit 3 - Sound 4 ON flag
Bit 2 - Sound 3 ON flag
Bit 1 - Sound 2 ON flag
Bit 0 - Sound 1 ON flag
Bits 0 - 3 of this register are meant to
be status bits to be read. Writing to
these bits does NOT enable/disable
sound.
If your GB programs don't use sound then
write $00 to this register to save 16%
or more on GB power consumption.
- Wave Pattern RAM
This storage area holds 32 4-bit samples
that are played back upper 4 bits first.
- LCDC (value $91 at reset)
2.13.1. I/O Registers
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