Nintendo DMG-01 - Game Boy Console Manual page 40

2.13.1. I/O Registers
interrupts are:
Interrupt
V-Blank
LCDC Status
Timer Overflow
Serial Transfer
Hi-Lo of P10-P13
* When more than 1 interrupts occur at the same
time only the interrupt with the highest priority
can be acknowledged. When an interrupt is used a
'0' should be stored in the IF register before the
IE register is set.
9. FF10 (NR 10)
Name
Contents - Sound Mode 1 register,
Page 40
Priority
- NR 10
Sweep register (R/W)
Bit 6-4 - Sweep Time
Bit 3 - Sweep Increase/Decrease
0: Addition (frequency increases)
1: Subtraction (frequency decreases)
Bit 2-0 - Number of sweep shift (n: 0-7)
Sweep Time:
000: sweep off - no freq change
001: 7.8 ms
010: 15.6 ms (2/128Hz)
011: 23.4 ms (3/128Hz)
Start Address
1 $0040
2 $0048 - Modes 0, 1, 2
3 $0050
4 $0058 - when transfer
5 $0060
(1/128Hz)
TM
Game Boy CPU Manual
LYC=LY coincide
(selectable)
is complete
V 1.01