Nintendo DMG-01 - Game Boy Console Manual page 38

2.13.1. I/O Registers
4. FF04 (DIV)
Name
Contents - Divider Register (R/W)
5. FF05 (TIMA)
Name
Contents - Timer counter (R/W)
Page 38
Bit 7 - Transfer Start Flag
0: Non transfer
1: Start transfer
Bit 0 - Shift Clock
0: External Clock (500KHz Max.)
1: Internal Clock (8192Hz)
Transfer is initiated by setting the
Transfer Start Flag. This bit may be read
and is automatically set to 0 at the end
of Transfer.
Transmitting and receiving serial data is
done simultaneously. The received data is
automatically stored in SB.
- DIV
This register is incremented 16384
(~16779 on SGB) times a second. Writing
any value sets it to $00.
- TIMA
This timer is incremented by a clock
frequency specified by the TAC register
($FF07). The timer generates an interrupt
when it overflows.
TM
Game Boy CPU Manual
V 1.01